IS43LD16640A Datasheet, PDF (31/143 Pages) Integrated Silicon Solution, Inc – Four-bit Pre-fetch DDR Architecture

IS43/46LD16640A
IS43/46LD32320A
Notes:
1. This table applies when: the previous state was self refresh or power-down; after tXSR z or tXP has been met; and both
CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
Idle: The bank has been precharged and tRP has been met.
Active: A row in the bank has been activated, tRCD has been met, no data bursts or accesses and no register accesses are in
progress.
Read: A READ burst has been initiated with auto precharge disabled and the READ has not yet terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE has not yet terminated or been termi-
nated.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. A BST command cannot be issued to another bank; it applies only to the bank represented by the current state.
6. The states listed below must not be interrupted by any executable command. NOP commands must be applied during
each clock cycle while in these states:
Idle MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device is
in the all banks idle state.
Reset MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device
is in the all banks idle state.
Active MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the bank is
in the active state.
MRW: Starts with registration of the MRW command and ends when tMRW has been met. After tMRW is met, the device is in
the all banks idle state.
7. BST is supported only if a READ or WRITE burst is ongoing.
8. tRRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m.
9. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled.
10. This command may or may not be bank-specific. If all banks are being precharged, they must be in a valid state for pre-
charging.
11. MRR is supported in the row-activating state.
12. MRR is supported in the precharging state.
13. The next state for bank m depends on the current state of bank m (idle, row-activating,precharging, or active).
14. A WRITE command can be issued after the completion of the READ burst; otherwise a BST must be issued to end the
READ prior to asserting a WRITE command.
15. A READ command can be issued after the completion of the WRITE burst; otherwise, a BST must be issued to end the
WRITE prior to asserting another READ command.
16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command
to other banks provided that the timing restrictions in the PRECHARGE and Auto Precharge Clarification table are met.
17. Not bank-specific; requires that all banks are idle and no bursts are in progress.
18. RESET command is achieved through MODE REGISTER WRITE command
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev. A
8/6/2014