IS43LD16640A Datasheet, PDF (23/143 Pages) Integrated Silicon Solution, Inc – Four-bit Pre-fetch DDR Architecture

IS43/46LD16640A
IS43/46LD32320A
MR48:62_(Reserved) (MA<7:0> = 030_H- 03E_H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR63_Reset (MA<7:0> = 03F_H): MRW only
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
X
Note: For additional information on MRW RESET, see “Mode Register Write Command” on Timing Spec.
MR64:126_(Reserved) (MA<7:0> = 040_H- 07E_H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR127_(Do Not Use) (MA<7:0> = 07F_H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
MR128:190_(Reserved for Vendor Use) (MA<7:0> = 080_H- 0BE_H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU
MR191_(Do Not Use) (MA<7:0> = 0BF_H):
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Do Not Use
Integrated Silicon Solution, Inc. — www.issi.com
23
Rev. A
8/6/2014