IS61VPD51236A Datasheet, PDF (28/29 Pages) Integrated Silicon Solution, Inc – 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

PACKAGING INFORMATION
Ball Grid Array
Package Code: B (165-pin)
ISSI^®
TOP VIEW
A1 CORNER
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A2
A
A1
BOTTOM VIEW
φ b (165X)
A1 CORNER
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
e
F
G
D D1
H
J
K
L
M
N
P
R
e
E1
E
BGA - 13mm x 15mm
MILLIMETERS
INCHES
Notes:
1. Controlling dimensions are in millimeters.
Sym. Min. Nom. Max.
N0.
Leads
165
A
—
— 1.20
A1
0.25 0.33 0.40
A2
— 0.79 —
D
14.90 15.00 15.10
D1 13.90 14.00 14.10
E
12.90 13.00 13.10
E1
9.90 10.00 10.10
e
— 1.00 —
b
0.40 0.45 0.50
Min. Nom. Max.
165
—
— 0.047
0.010 0.013 0.016
— 0.031 —
0.587 0.591 0.594
0.547 0.551 0.555
0.508 0.512 0.516
0.390 0.394 0.398
— 0.039 —
0.016 0.018 0.020
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
06/11/03