IS61VPD51236A Datasheet, PDF (14/29 Pages) Integrated Silicon Solution, Inc – 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

IS61VPD51236A, IS61VPD102418A,IS61LPD51236A,IS61LPD102418A
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-250
Min. Max.
-200
Min. Max.
Unit
fMAX Clock Frequency
—
250
—
200
MHz
tKC
Cycle Time
4.0
—
5
—
ns
tKH
Clock High Time
1.7
—
2
—
ns
tKL
Clock Low Time
1.7
—
2
—
ns
tKQ
Clock Access Time
—
2.6
—
3.1
ns
tKQX⁽²⁾ Clock High to Output Invalid
0.8
—
1.5
—
ns
tKQLZ^(2,3) Clock High to Output Low-Z
0.8
—
1
—
ns
tKQHZ^(2,3) Clock High to Output High-Z
—
2.6
—
3.0
ns
tOEQ Output Enable to Output Valid
—
2.6
—
3.1
ns
tOELZ^(2,3) Output Enable to Output Low-Z
0
—
0
—
ns
tOEHZ^(2,3) Output Disable to Output High-Z
—
2.6
—
3.0
ns
tAS
Address Setup Time
1.2
—
1.4
—
ns
tWS Read/Write Setup Time
1.2
—
1.4
—
ns
tCES Chip Enable Setup Time
1.2
—
1.4
—
ns
tAVS Address Advance Setup Time
1.2
—
1.4
—
ns
tDS
Data Setup Time
1.2
—
1.4
—
ns
tAH
Address Hold Time
0.3
—
0.4
—
ns
tWH Write Hold Time
0.3
—
0.4
—
ns
tCEH Chip Enable Hold Time
0.3
—
0.4
—
ns
tAVH Address Advance Hold Time
0.3
—
0.4
—
ns
tDH
Data Hold Time
0.3
—
0.4
—
ns
tPDS ZZ High to Power Down
—
2
—
2
cyc
tPUS ZZ Low to Power Down
—
2
—
2
cyc
Note:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/03/06