IS61VPD51236A Datasheet, PDF (22/29 Pages) Integrated Silicon Solution, Inc – 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

IS61VPD51236A, IS61VPD102418A,IS61LPD51236A,IS61LPD102418A
ISSI ^®
TAP Electrical Characteristics Over the Operating Range^(1,2)
Symbol
Parameter
Test Conditions
VOH1
Output HIGH Voltage
IOH = –2.0 mA
VOH2
Output HIGH Voltage
IOH = –100 µA
VOL1
Output LOW Voltage
IOL = 2.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
Vss ≤ V I ≤ VDDQ
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot:VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Min.
1.7
2.1
—
—
1.7
–0.3
–5
Max.
—
—
0.7
0.2
VDD +0.3
0.7
5
Units
V
V
V
V
V
V
mA
TAP AC ELECTRICAL CHARACTERISTICS^(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
tTCYC TCK Clock cycle time
100
fTF
TCK Clock frequency
—
tTH
TCK Clock HIGH
40
tTL
TCK Clock LOW
40
tTMSS TMS setup to TCK Clock Rise
10
tTDIS
TDI setup to TCK Clock Rise
10
tCS
Capture setup to TCK Rise
10
tTMSH TMS hold after TCK Clock Rise
10
tTDIH
TDI Hold after Clock Rise
10
tCH
Capture hold after Clock Rise
10
tTDOV TCK LOW to TDO valid
—
tTDOX TCK LOW to TDO invalid
0
Notes:
1. Both tCS and tCH refer to the set-up and hold time latching data requirements from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/03/06