IS66WVE2M16ALL Datasheet, PDF (21/30 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66WVE2M16ALL
IS67WVE2M16ALL
Table 9 . Asynchronous WRITE Cycle Timing Requirements
Symbol
Parameter
t_AS
Address setup Time
t_AW
Address valid to end of write
t_BW
Byte select to end of write
t_CPH CE# HIGH time during write
t_CW
Chip enable to end of Write
t_DH
Data hold from write time
t_DW
Data write setup time
t_LZ
Chip enable to Low-Z output
t_OW
End write to Low-Z output
t_WC
Write cycle time
t_WHZ Write to High-Z output
t_WP
Write pulse width
t_WPH Write pulse width HIGH
t_WR
Write recovery time
-70
Unit
Min
Max
0
ns
70
ns
70
ns
5
ns
70
ns
0
ns
23
ns
10
ns
5
ns
70
ns
8
ns
46
ns
10
ns
0
ns
Notes
1
1
2
3
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. WE# LOW must be limited to t_CEM (8us)
Rev. B | Jan. 2012
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