IS93C56A Datasheet, PDF (16/16 Pages) Integrated Silicon Solution, Inc – 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM

PACKAGING INFORMATION
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
ISSI^®
N
E1 E
1
N/2
D
A2
e
B
α
A1
A
L
C
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
8
Millimeters
Inches
Symbol Min Max Min Max
A — 1.20
— 0.047
A1 0.05 0.15
A2 0.80 1.05
0.002 0.006
0.032 0.041
B 0.19 0.30 0.007 0.012
C 0.09 0.20 0.004 0.008
D 2.90 3.10 0.114 0.122
E1 4.30 4.50 0.169 0.177
E
6.40 BSC
e
0.65 BSC
0.252 BSC
0.026 BSC
L 0.45 0.75 0.018 0.030
α — 8°
— 8°
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
14
Millimeters
Inches
Symbol Min Max Min Max
A — 1.20
— 0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.031 0.041
B 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 4.90 5.10 0.193 0.201
E1 4.30 4.50 0.170 0.177
E 6.40 BSC
0.252 BSC
e 0.65 BSC
0.026 BSC
L 0.45 0.75 0.0177 0.0295
α — 8°
— 8°
SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev B 02/01/02