IS61WV25632ALL Datasheet, PDF (15/19 Pages) Integrated Silicon Solution, Inc – TTL compatible inputs and outputs

IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4 (Byte Controlled, Back-to-Back Write) ^(1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
OE
CE _LOW
t SA
WE
BWa-d
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1.  The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be
deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the
Write.
2.  Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev.  00B
04/23/08