IS61WV25632ALL Datasheet, PDF (12/19 Pages) Integrated Silicon Solution, Inc – TTL compatible inputs and outputs

IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)

Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
-20 ns
Min. Max. Unit
20 — ns
12 — ns
taw

Address Setup Time
to Write End
12 — ns
tha
Address Hold from Write End
0
— ns
tsa
tpwb
tpwe1
tpwe2
Address Setup Time
BWa-d Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
0
— ns
12 — ns
12 — ns
17 — ns
tsd
thd
thzwe⁽³⁾
tlzwe⁽³⁾
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
9
— ns
0 — ­ns
—
9 ns
3 — ns
Notes:
1.  Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup
and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
04/23/08