IS61SP6464 Datasheet, PDF (15/20 Pages) Integrated Silicon Solution, Inc – 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

IS61SP6464
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-6 ns
Min. Max.
tKC
Cycle Time
12 —
tKH
Clock High Time
4.5 —
tKL
Clock Low Time
4.5 —
tKQ
Clock Access Time
—
6
tKQX⁽¹⁾ Clock High to Output Invalid
2.5 —
tKQLZ^(1,2) Clock High to Output Low-Z
0
—
tKQHZ^(1,2) Clock High to Output High-Z
2
5
tOEQ
Output Enable to Output Valid
—
5
tOEQX⁽¹⁾ Output Disable to Output Invalid
0
—
tOELZ^(1,2) Output Enable to Output Low-Z
0
—
tOEHZ^(1,2) Output Disable to Output High-Z
2
5
tAS
Address Setup Time
2.5 —
tSS
Address Status Setup Time
2.5 —
tWS
Write Setup Time
2.5 —
tCES
Chip Enable Setup Time
2.5 —
tAH
Address Hold Time
0.5 —
tSH
Address Status Hold Time
0.5 —
tWH
Write Hold Time
0.5 —
tCEH
Chip Enable Hold Time
0.5 —
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
-7 ns
Min. Max.
13 —
5
—
5
—
—
7
3
—
0
—
2
5
—
5
0
—
0
—
2
5
2.5 —
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
0.5 —
-8 ns
Min. Max. Unit
15
—
ns
6
—
ns
6
—
ns
—
8
ns
3
—
ns
0
—
ns
2
6
ns
—
5
ns
0
—
ns
0
—
ns
2
6
ns
2.5 —
ns
2.5 —
ns
2.5 —
ns
2.5 —
ns
0.5 —
ns
0.5 —
ns
0.5 —
ns
0.5 —
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
04/17/01