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IS61SP6464 Datasheet, PDF (14/20 Pages) Integrated Silicon Solution, Inc – 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM | |||
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IS61SP6464
ISSI ®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-133 MHz
Min. Max.
tKC
Cycle Time
7.5 â
tKH
Clock High Time
3
â
tKL
Clock Low Time
3
â
tKQ
Clock Access Time
â
5
tKQX(1) Clock High to Output Invalid
1.5 â
tKQLZ(1,2) Clock High to Output Low-Z
0
â
tKQHZ(1,2) Clock High to Output High-Z
1.5 7.5
tOEQ
Output Enable to Output Valid
â
5
tOEQX(1) Output Disable to Output Invalid
0
â
tOELZ(1,2) Output Enable to Output Low-Z
0
â
tOEHZ(1,2) Output Disable to Output High-Z
â
â
tAS
Address Setup Time
2.5 â
tSS
Address Status Setup Time
2.5 â
tWS
Write Setup Time
2.5 â
tCES
Chip Enable Setup Time
2.5 â
tAH
Address Hold Time
0.5 â
tSH
Address Status Hold Time
0.5 â
tWH
Write Hold Time
0.5 â
tCEH
Chip Enable Hold Time
0.5 â
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
-117 MHz
Min. Max.
8.5 â
3.4 â
3.4 â
â
5
1.5 â
0
â
1.5 8.5
â
5
0
â
0
â
â
â
2.5 â
2.5 â
2.5 â
2.5 â
0.5 â
0.5 â
0.5 â
0.5 â
-100 MHz
Min. Max. Unit
10
â
ns
4.
â
ns
4
â
ns
â
5
ns
2.5 â
ns
0
â
ns
2
5
ns
â
5
ns
0
â
ns
0
â
ns
2
5
ns
2.5 â
ns
2.5 â
ns
2.5 â
ns
2.5 â
ns
0.5 â
ns
0.5 â
ns
0.5 â
ns
0.5 â
ns
14
Integrated Silicon Solution, Inc. â 1-800-379-4774
Rev. A
04/17/01
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