IS61WV20488ALL_10 Datasheet, PDF (12/19 Pages) Integrated Silicon Solution, Inc – 2M x 8 HIGH-SPEED CMOS STATIC RAM

IS61WV20488ALL, IS61/64WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwe1
tpwe2
tsd
thd
thzwe⁽³⁾
tlzwe⁽³⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-20 ns
Min. Max. Unit
20 —
ns
12 —
ns
12 —
ns
0—
ns
0—
ns
12 — ns
17 —
ns
9—
ns
0—
­ns
—9
ns
3—
ns
Notes:
1.  Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  B
08/04/2010