IS64LV51216 Datasheet, PDF (11/15 Pages) Integrated Silicon Solution, Inc – 512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV51216
IS64LV51216
ISSI ^®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ^(1,3)
1
t WC
t WC
ADDRESS
ADDRESS 1
ADDRESS 2
2
OE
t SA
CE _LOW
t HA
t HA
3
WE
t SA
t PBW
t PBW
UB, LB
WORD 1
WORD 2
4
t HZWE
t LZWE
DOUT DATA UNDEFINED
HIGH-Z
t SD
t HD
t SD
t HD
5
DIN
DATAIN
VALID
DATAIN
VALID
UB_CEWR4.eps
6 ^Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. D
12/06/05