IS61WV10248EDBLL Datasheet, PDF (11/18 Pages) Integrated Silicon Solution, Inc – TTL compatible inputs and outputs

IS61WV10248EDBLL
IS64WV10248EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)

Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time
to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
tpwe1
WE Pulse Width (OE = HIGH)
tpwe2
WE Pulse Width (OE = LOW)
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe⁽²⁾
WE LOW to High-Z Output
tlzwe⁽²⁾
WE HIGH to Low-Z Output
-20 ns
Min. Max. Unit
20 —
ns
12 —
ns
12 —
ns
0—
ns
0—
ns
12 —
ns
17 —
ns
9—
ns
0—
­ns
—9
ns
3—
ns
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test
Loads (Figure 1).
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. A
02/20/2013