IS61WV10248EDBLL Datasheet, PDF (10/18 Pages) Integrated Silicon Solution, Inc – TTL compatible inputs and outputs

IS61WV10248EDBLL
IS64WV10248EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
-8
-10
Parameter Min. Max. Min. Max. Unit
twc
Write Cycle Time
8
—
10 —
ns
tsce
CE to Write End
6.5 —
8
—
ns
taw
Address Setup Time
to Write End
6.5 —
8
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwe1
WE Pulse Width (OE = HIGH)
6.5 —
8
—
ns
tpwe2
WE Pulse Width(OE = LOW)
8.0 —
10 —
ns
tsd
Data Setup to Write End
5
—
6
—
ns
thd
Data Hold from Write End
0
—
0
—
­ns
thzwe⁽²⁾ WE LOW to High-Z Output
— 3.5
—
5
ns
tlzwe⁽²⁾ WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/20/2013