IRF8113 Datasheet, PDF (8/10 Pages) International Rectifier – Power MOSFET

IRF8113
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R_ds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P_loss = P + _conduction P + _switching P_drive+ P_output
This can be expanded and approximated by;
( ) P_loss =
I2
rms
×
R_{ds(on )}

+I

×
Q_gd
i_g
× V_in
×
f ^


+I

×
Q_{gs 2}
i_g
× V_in
×
f 

( ) + Q_g × V_g × f
+


Q_oss
2
× V_in
×
f


This simplified loss equation includes the terms Q_gs2
and Q_oss which are new to Power MOSFET data sheets.
Q_gs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q_gs1 and Q_gs2, can be seen from
Fig 16.
Q_gs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I_dmax at which time the drain voltage be-
gins to change. Minimizing Q_gs2 is a critical factor in
reducing switching losses in Q1.
Q_oss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q_oss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C_ds and C_dg when multiplied by
the power supply input buss voltage.
8
Synchronous FET
The power loss equation for Q2 is approximated
by;
P_loss
=
P_conduction
+
P_drive
+
P*
output
( ) ^Ploss ⁼
2
I_rms
×
R_ds(on)
( ) + Q_g × V_g × f
( ) +  Qoss
2
× V_in ×
f^ +

Q_rr × V_in ×
f
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R_ds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q_oss and re-
verse recovery charge Q both generate losses that
rr
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V_in. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q_gd/Q_gs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Q_oss Characteristic
www.irf.com