IRF7907PBF_08 Datasheet, PDF (8/10 Pages) International Rectifier – Dual SO-8 MOSFET for POL

IRF7907PbF
+
‚
-

R_G
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-^„ +
D.U.T. I_SD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V_DS Waveform _{Diode Recovery}
dv/dt
• dv/dt controlled by R_G
• Driver same type as D.U.T.
V_DD
+
• I_SD controlled by Duty Factor "D"
-
• D.U.T. - Device Under Test
Re-Applied
Voltage
Body Diode
I_In_nd_du_uc_ct_to_or_{r C}C_uu_rr_ere_nn_t t
Forward Drop
Ripple ≤ 5%
* V_GS = 5V for Logic Level Devices
Fig 28. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET^® Power MOSFETs
* V_GS=10V
V_DD
I_SD
V_(BR)DSS
15V
tp
VDS
L
DRIVER
RG
2V0GVS
tp
D.U.T
I_AS
0.01Ω
+
- ^VDD
A
Fig 29a. Unclamped Inductive Test Circuit
I_AS
Fig 29b. Unclamped Inductive Waveforms
15V
VDS
L
DRIVER
RG
20V
tp
D.U.T
I_AS
0.01Ω
+
- ^VDD
A
Fig 30a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
-
+VDS
V_GS
-3mA
I_G
I_D
Current Sampling Resistors
Fig 31a. Gate Charge Test Circuit
8
V_DS
90%
10%
V_GS
t_{d(on) tr}
t_{d(off) tf}
Fig 30b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2 Qgd
Qgodr
Fig 31b. Gate Charge Waveform
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