IRF7759L2PBF_15 Datasheet, PDF (6/11 Pages) International Rectifier – Optimized for Synchronous Rectification

IRF7759L2PbF
1000
100
10
Duty Cycle = Single Pulse
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
300
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
250
ID = 96A
200
150
100
50
0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T_jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT_jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 19a, 19b.
4. P_{D (ave)} = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I_av = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
T_jmax (assumed as 25°C in Figure 15, 16).
t_{av =} Average time in avalanche.
D = Duty cycle in avalanche = t_av ·f
Z_thJC(D, t_av) = Transient thermal resistance, see figure 11)
P_{D (ave)} = 1/2 ( 1.3·BV·I_av) = DT/ Z_thJC
I_av = 2DT/ [1.3·BV·Z_th]
E_{AS (AR)} = P_{D (ave)}·t_a
+
‚
-

R_G
D.U.T
+
ƒ
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-^„ +
• di/dt controlled by R_G
• Driver same type as D.U.T.
V_DD
+
• I_SD controlled by Duty Factor "D"
-
• D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
* V_GS=10V
D.U.T. I_SD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. V_DS Waveform
Diode Recovery
dv/dt
V_DD
Re-Applied
Voltage
Body Diode
IInndduuccttoorr CCuurrernetnt
Forward Drop
Ripple ≤ 5%
I_SD
* V_GS = 5V for Logic Level Devices
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET^® Power MOSFETs
6
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February 24, 2014