IRF7901D1 Datasheet, PDF (3/8 Pages) International Rectifier – Dual FETKY™ Co-Packaged Dual MOSFET Plus Schottky Diode

IRF7901D1
Power MOSFET Optimization for DC-DC Converters
Table 1 and Table 2 describes the event during the various charge segments and shows an approximation of losses during
that period.
Table 1 – Control FET Losses
Description
Segment Losses
Conduction Losses associated with MOSFET on time. I_RMS is a function of load
Loss current and duty cycle.
P _COND
=
I
2
RMS
×
R _{DS (on)}
Gate Drive
Loss
Switching
Loss
Losses associated with charging and discharging the gate of the
MOSFET every cycle. Use the control FET Q_G.
Losses during the drain voltage and drain current transitions for every full
cycle.
Losses occur during the Q_GS2 and Q_GD time period and can be simplified by
using Q_switch.
P_IN = V_G × Q_G × ƒ
P
QGS 2
≈
V
IN
×
I
L
× ^{Q GS 2}
I
׃
G
Q
P_QGD ≈ V_IN × I_L ×
GD _{× ƒ}
I
G
Output
Loss
Losses associated with the Q_OSS of the device every cycle when the control
FET turns on. Losses are caused by both FETs, but are dissipated by the
control FET.
Q
P
SWITCH
≈
V
IN
×
I
L
SW _{× ƒ}
I
G
P_OUTPUT =
Q_OSS
2
× V_IN
×
ƒ
Table 2 – Synchronous FET Losses
Description
Segment Losses
Conduction Losses associated with MOSFET on time. I_RMS is a function of load current and
Loss duty cycle.
P_COND = I_RMS² × R_DSon
Gate Drive Losses associated with charging and discharging the gate of the MOSFET
Loss every cycle. Use the Sync FET Q_G.
Switching Generally small enough to ignore except at light loads when the current
Loss reverses in the output inductor. Under these conditions various light load
power saving techniques are employed by the control IC to maintain switching
losses to a negligible level.
P_IN = V_G × Q_G × ƒ
P_SWITCH ≈ 0
P_OUTPUT
=
Q_OSS
2
×
V_IN
×
ƒ
Output
Loss
Losses associated with the Q_OSS of the device every cycle when the control FET
turns on. They are caused by the synchronous FET, but are dissipated in the
control FET.
Typical Application
The performance of the new Dual FETKY^TM has been tested in-circuit using IR’s new IRNBPS2 “Dual Output
Synchronous Buck Design Kit”, operating up to 21V_in and 5A peak output current, with operating voltages from
1V_out to 5V_out.
Pin 7&8
Pwr Vin
Pin 1
Q1 Source
Pin 5&6
Pwr Vout
Shaded area = Dual FETKY
Q1 _{Pin 2}
Vin
Q1 Gate Q2
Vout
Pin 3
PGND
Pin 4
Q2 Gate
Schottky
Figure 1: Synchronous Buck dc-dc
Topology
www.irf.com
3