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X98024 Datasheet, PDF (9/29 Pages) Intersil Corporation – 240MHz Triple Video Digitizer with Digital PLL
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X98024
Pin Descriptions
SYMBOL
PIN
RIN1
7
GIN1
12
BIN1
19
RGBGND1
13
SOGIN1
14
HSYNCIN1
33
VSYNCIN1
44
RIN2
22
GIN2
24
BIN2
28
RGBGND2
25
SOGIN2
26
HSYNCIN2
34
VSYNCIN2
45
CLOCKINVIN
41
RESET
XTALIN
XTALOUT
XTALCLKOUT
SADDR
SCL
SDA
RP[7:0]
RS[7:0]
GP[7:0]
GS[7:0]
BP[7:0]
BS[7:0]
DATACLK
DATACLK
46
39
40
47
48
50
49
112-119
100-107
90-97
80-87
68-75
55-62
121
122
DESCRIPTION
Analog input. Red channel 1. DC couple or AC couple through 0.1µF.
Analog input. Green channel 1. DC couple or AC couple through 0.1µF.
Analog input. Blue channel 1. DC couple or AC couple through 0.1µF.
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GNDA.
Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500Ω resistor.
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GNDA. Connect to channel 1's HSYNC
signal through a 680Ω series resistor.
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
Analog input. Red channel 2. DC couple or AC couple through 0.1µF.
Analog input. Green channel 2. DC couple or AC couple through 0.1µF.
Analog input. Blue channel 2. DC couple or AC couple through 0.1µF.
Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GNDA.
Analog input. Sync on Green. Connect to GIN1 through a 0.01µF capacitor in series with a 500Ω resistor.
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GNDA. Connect to channel 2's HSYNC
signal through a 680Ω series resistor.
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame
rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to
DGND if unused.
Digital input, 5V tolerant, active low, 70kΩ pull-up to VD. Take low for at least 1µs and then high again to
reset the X98024. This pin is not necessary for normal use and may be tied directly to the VD supply.
Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.
Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for
recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.
3.3V digital output. Buffered crystal clock output at fXTAL or fXTAL/2. May be used as system clock for other
system components.
Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A
including R/W bit) when tied high.
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
3.3V digital output. Red channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated.
3.3V digital output. Green channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated.
3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated.
3.3V digital output. Blue channel, secondary pixel data. 58K pulldown when three-stated.
3.3V digital output. Data clock output. Equal to pixel clock rate in 24 bit mode, one half pixel clock rate in 48
bit mode.
3.3V digital output. Inverse of DATACLK.
9
FN8220.0
June 6, 2005
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