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| X98024 Datasheet, PDF (6/29 Pages) Intersil Corporation – 240MHz Triple Video Digitizer with Digital PLL | |||
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HSYNCIN
Analog
Video In
DATACLK
RP/GP/BP[7:0]
RS/GS/BS[7:0]
HSOUT
HSYNCIN
Analog
Video In
DATACLK
GP[7:0]
RP[7:0]
BP[7:0]
HSOUT
X98024
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFEâs output signals
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
8.5 DATACLK Pipeline Latency
D0
D1
D2
D3
Programmable
Width and Polarity
FIGURE 3. 24 BIT OUTPUT MODE
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFEâs output signals
tHSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
8.5 DATACLK Pipeline Latency
G0 (Yo) G1 (Y1) G2 (Y2)
B0 (Uo) R1 (V1) B2 (U2)
Programmable
Width and Polarity
FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
6
FN8220.0
June 6, 2005
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