X98024 Datasheet, PDF (10/29 Pages) Intersil Corporation – 240MHz Triple Video Digitizer with Digital PLL

X98024
Pin Descriptions (Continued)
SYMBOL
PIN
DESCRIPTION
HS_OUT
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
VS_OUT
HSYNC_OUT
VSYNC_OUT
126
3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HS_OUT. This signal is usually not needed - use VSYNC_OUT as VSYNC source.
127
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HS_OUT should be used to detect the beginning of a line. This output will pass composite sync signals
and Macrovision signals if present on HSYNC_IN or SOG_IN.
128
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
V_A
6, 11, 18, 20, Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND_A with 0.1µF.
29, 35
GND_A
3, 5, 8, 10, 15, Ground return for V_A and V_BYPASS.
17, 21, 23, 27,
30, 36
V_D
54, 67, 77, 89, Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND_D with 0.1µF.
99, 111, 124
GND_D
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for V_D, V_CORE, V_COREADC, and V_PLL.
V_X
GND_X
V_BYPASS
VREG_IN
VREG_OUT
V_COREADC
V_PLL
38
37
4, 9, 16
65
64
31
42
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND_X with 0.1µF.
Ground return for V_X.
Bypass these pins to GND_A with 0.1µF. Do not connect these pins to each other or anything else.
3.3V input voltage for V_CORE voltage regulator. Connect to a 3.3V source, and bypass to GND_D with 0.1µF.
Regulated output voltage for V_PLL, V_COREADC and V_CORE; typically 1.9V. Connect only to V_PLL,
V_COREADC and V_CORE and bypass at input pins as instructed below. Do not connect to anything else - this
output can only supply power to V_PLL, V_COREADC and V_CORE.
Internal power for the ADC’s digital logic. Connect to VREG_OUT through a 10Ω resistor and bypass to GND_D
with 0.1µF.
Internal power for the PLL’s digital logic. Connect to VREG_OUT through a 10Ω resistor and bypass to GND_D
with 0.1µF.
V_CORE
NC
52, 79, 109
1, 2, 63
Internal power for core logic. Connect to VREG_OUT and bypass each pin to GND_D with 0.1µF.
Reserved. Do not connect anything to these pins.
10
FN8220.0
June 6, 2005