X9522_06 Datasheet, PDF (9/27 Pages) Intersil Corporation – Triple DCP, Dual Voltage Monitors

X9522
Signals from
the Master
SDA Bus
Signals from
the Slave
WRITE Operation
READ Operation
S
S
t
a
r
Slave
Address
Instruction
Byte
t
a
r
Slave
Address
S
t
Data Byte o
t
t
p
10101110
W
T
00000
P
1
P
0
10101111
A
A
A
C
C
C
K
K
K
“Dummy” write
Figure 10. DCP Read Sequence
DCPx
--
x=0
-
x=1
MSB
LSB
“-” = DON’T CARE
x=2
It should be noted that all writes to any DCP of the X9522
are random in nature. Therefore, the Data Byte of con-
secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits P1=1, P0=1
is a reserved sequence, and will result in no ACKNOWL-
EDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R_WX (x = 0,1,2) at
the “lowest” tap position, Therefore, the resistance
between R_WX and R_LX is a minimum (essentially only the
Wiper Resistance, R_W).
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9522 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9522.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9522
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
It should be noted that when reading out the data byte
for DCP0 (64 Tap), the upper two most significant bits
are “unknown” bits. For DCP1 (100 Tap), the upper
most significant bit is an “unknown”. For DCP2 (256
Tap) however, all bits of the data byte are relevant (See
Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro-
vides the user with a mechanism for changing and
reading the status of various parameters of the
X9522 (See Figure 11).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when Vcc /
V1 is powered down, then powered back up. The volatile
bits however, will always power-up to a known logic state
“0” (irrespective of their value at power-down).
9
FN8208.1
January 3, 2006