X9522_06 Datasheet, PDF (11/27 Pages) Intersil Corporation – Triple DCP, Dual Voltage Monitors

X9522
SCL
SDA
S 1 0 1 0 0 1 0 R/W A 1
T
C
A
K
R
T
SLAVE ADDRESS BYTE
1 11 1 1 1 1
ADDRESS BYTE
A CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A S
C
CT
K
KO
CONSTAT REGISTER DATA IN
P
Figure 12. CONSTAT Register Write Command Sequence
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK bit. The
X9522 will not ACKNOWLEDGE any data bytes written
after the first byte is entered (Refer to Figure 12.).
When writing to the CONSTAT register, the bits CS7,
CS4 and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7, CS4 and CS0 of the CONSTAT
register is reserved.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps:
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the
Register Write Enable Latch (RWEL) AND the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceded by a START
and ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 0xy0t010 in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, and t is the DCP Write Lock
(DWLK) bit. This operation is proceeded by a START
and ended with a STOP bit. Since this is a nonvolatile
write cycle, it will typically take 5ms to complete. The
RWEL bit is reset by this cycle and the sequence must
be repeated to change the nonvolatile bits again. If bit
2 is set to ‘1’ in this third step (0xy0 t110) then the
RWEL bit is set, but the DWLK bit will remain
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and the X9522 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation
READ Operation
S
Address
t
a ^Slave
S
t
Byte
r Address
o
t
p
CS7 … CS0
10 1 0 0 1 0 0
10 1 0 0 101
A
A
C
C
K
K
A
C
K
Data
“Dummy” Write
Figure 13. CONSTAT Register Read Command Sequence
11
FN8208.1
January 3, 2006