X4003 Datasheet, PDF (9/17 Pages) Xicor Inc. – CPU Supervisor

X4003, X4005
Serial Read Operations
The read operation allows the master to access the control
register. To conform to the I²C standard, prior to issu-
ing the slave address byte with the R/W bit set to one,
the master must first perform a “dummy” write opera-
tion. The master issues the start condition and the
slave address byte, receives an acknowledge, then
issues the byte address. After acknowledging receipt
of the byte address, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit control
register. The master terminates the read operation by
not responding with an acknowledge and then issuing
a stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
RESET/RESET signal is active for t_PURST.
Figure 9. Control Register Read Sequence
S
Signals from
t
Slave
the Master
a
r
Address
t
Byte
Address
S
t
Slave
a
r
Address
t
S
t
o
p
SDA Bus
1 0 11 0 010 1 1 1 1111 1 10 1 10 01 1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow a write operation.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
– The WP pin, when held HIGH, prevents all writes to
the control register.
– Communication to the device is inhibited below the
V_TRIP voltage.
– Command to change the control register are termi-
nated if in-progress when RESET/RESET go active.
Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
9
FN8113.0
March 15, 2005