X4003 Datasheet, PDF (5/17 Pages) Xicor Inc. – CPU Supervisor

X4003, X4005
Figure 4. V_TRIP Programming Sequence
V_TRIP Programming
Execute
Reset V_TRIP
Sequence
Set V_CC = V_CC Applied =
Desired V_TRIP
New V_CC Applied =
Old V_CC Applied - Error
Execute
Reset V_TRIP
Sequence
Execute
Set V_TRIP
Sequence
Apply 5V to V_CC
Decrement V_CC
(V_CC = V_CC - 50mV)
New V_CC Applied =
Old V_CC applied + Error
RESET pin
goes active?
YES
Error ≥ Emax
Measured V_TRIP -
Desired V_TRIP
-Emax < Error < Emax
DONE
NO
Error ≤ –Emax
Emax = Maximum Allowable V_TRIP Error
Control Register
The control register provides the user a mechanism
for changing the watchdog timer settings. watchdog
timer bits are nonvolatile and do not change when
power is removed.
The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a control register
write operation. Only one data byte is allowed for each
register write operation. Prior to writing to the control reg-
ister, the WEL and RWEL bits must be set using a two
step process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register" below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
76 5 4
0 WD1 WD0 0
3
2
10
0 RWEL WEL 0
5
FN8113.0
March 15, 2005