X4003 Datasheet, PDF (2/17 Pages) Xicor Inc. – CPU Supervisor

PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
NC ¹
NC 2
RESET ³
V_SS 4
8 V_CC
7 _WP
6 SCL
5 SDA
X4003, X4005
PIN DESCRIPTION
Pin
(SOIC/DIP)
1
2
3
Pin
TSSOP
3
4
5
4
6
5
7
6
8
7
1
8
2
Pin
(MSOP)
2
3
4
5
6
1
Name
NC
NC
RESET/
RESET
V_SS
SDA
SCL
WP
V_CC
Function
No internal connections
No internal connections
Reset Output. RESET/RESET is an active LOW/HIGH, open
drain output which goes active whenever V_CC falls below the min-
imum V_CC sense level. It will remain active until V_CC rises above
the minimum V_CC sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA re-
mains either HIGH or LOW longer than the selectable Watchdog
time out period. A falling edge of SDA, while SCL also toggles from
HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET/RESET goes active on power-
up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into
and out of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. This pin re-
quires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while
SCL also toggles from HIGH to LOW follow by a stop condition re-
sets the watchdog timer. The absence of this procedure within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The serial clock controls the serial bus timing for
data input and output.
Write Protect. WP HIGH prevents changes to the watchdog
timer setting.
Supply voltage
2
FN8113.0
March 15, 2005