X28HC256 Datasheet, PDF (9/15 Pages) Xicor Inc. – 5 Volt, Byte Alterable E2PROM

X28HC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V_CC
Data
Address
CE
AAA
55
80
AA
55
20
5555
2AAA
5555
5555
2AAA
5555
t_WC
WE
Standard
Operating
Mode
Figure 9. Write Sequence for resetting Software
Data Protection
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 80
to Address
5555
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
After t_WC,
Re-Enters
Unprotected
State
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t_WC,
the X28HC256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large
memory arrays, it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC256 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the l/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between V_CC and V_SS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V_CC and V_SS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
9
FN8108.1
May 17, 2006