ISL7457SRH Datasheet, PDF (9/12 Pages) Intersil Corporation – Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver

ISL7457SRH
Application Information
Product Description
The ISL7457SRH is a high performance, high speed quad
CMOS driver. Each channel of the ISL7457SRH consists of
a single P-channel high side driver and a single N-Channel
low side driver. These 3.5Ω devices will pull the output
(OUTx) to either the high or low voltage, on V_H and V_L
respectively, depending on the input logic signal (INx). It
should be noted that there is only one set of high and low
voltage pins.
A common output enable (OE) pin is available on the
ISL7457SRH. When this pin is pulled low, it will put all
outputs in a high impedance state.
Supply Voltage Range and Input Compatibility
The ISL7457SRH is designed to operate on nominal 5V to
15V supplies with ±10% tolerance. Table 1 on page 7 shows
the specifications for the relationship between the V_S+, V_S-,
V_H, V_L, and GND pins. The ISL7457SRH does not contain a
true analog switch and therefore V_L should always be less
than V_H.
All input pins are compatible with both 3.3V and 5V CMOS
signals.
PCB Layout Guidelines
1. A ground plane must be used, preferably located on layer
#2 of the PCB.
2. Connect the GND and V_S- pins directly to the ground
plane.
2. The V_S+, V_H and V_L pins should be bypassed directly to
the ground plane using a low-ESR, 4.7µF solid tantalum
capacitor in parallel with a 0.1µF ceramic capacitor. Locate
all bypass capacitors as close as possible to the respective
pins of the IC.
3. Keep all input and output connections to the IC as short as
possible.
4. For high frequency operation above 1MHz, consider use
of controlled impedance traces terminated into 50Ω on all
inputs and outputs.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
ISL7457SRH drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
T_JMAX (+150°C).
Power dissipation may be calculated as shown in
Equation 1:
4
∑ ^PD ^{= (V}S ^{× I}S^{) + (C}INT ^{× V}S2 ^{× f) + (C}L ^{× V}O2 UT ^{× f)}
1
(EQ. 1)
where:
P_D is the power dissipated in the device.
V_S is the total power supply to the ISL7457SRH (from V_S+
to V_S-).
I_S is the quiescent supply current.
C_INT is the internal load capacitance (80pF max).
f is the operating frequency.
C_L is the load capacitance.
V_OUT is the swing on the output (V_H - V_L).
Junction Temperature Calculation
Once the power dissipation for the application is determined,
the maximum junction temperature can be calculated as
shown in Equation 2:
T_JMAX = T_SMAX + (Θ_JC + Θ_CS ) × P_D
(EQ. 2)
where:
T_JMAX is the maximum operating junction temperature
(150°C).
T_SMAX is the maximum operating sink temperature of the
PCB.
θ_JC is the thermal resistance, junction-to-case, of the
package.
θ_CS is the thermal resistance, case-to-sink, of the PCB.
P_D is the power dissipation calculated in Equation 1.
PCB Thermal Management
To minimize the case-to-sink thermal resistance, it is
recommended that multiple vias be placed on the top layer
of the PCB directly underneath the IC. The vias should be
connected to the ground plane, which functions as a
heatsink. A gap filler material (i.e. a Sil-Pad or thermally
conductive epoxy) may be used to insure good thermal
contact between the bottom of the IC and the vias.
9
FN6874.0
March 16, 2009