ISL6557A Datasheet, PDF (9/19 Pages) Intersil Corporation – Multi-Phase PWM Controller for Core-Voltage Regulation

ISL6557A
system remains in this state while the controller counts 2048
phase-clock cycles.
V_COMP
+
-
f(jω)
+
-
SAWTOOTH SIGNAL
I_ER
I_{AVG ÷ N}
Σ
-
+
PWM1
I₄ *
I₃ *
I₂
I₁
FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
NOTE: *Channels 3 and 4 are optional.
This is followed by a soft-start attempt (see Soft-Start). If the
soft-start attempt is successful, operation will continue as
normal. Should the soft-start attempt fail, the ISL6557A
repeats the 2048-cycle wait period and follows with another
soft-start attempt. This hiccup mode of operation continues
indefinitely as shown in Figure 6 as long as the controller is
enabled or until the overcurrent condition resolves.
OUTPUT CURRENT, 20A/DIV
0A
OUTPUT VOLTAGE,
500mV/DIV
0V
5ms/DIV
FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE
VOLTAGE REGULATION
The ISL6557A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
pins VID4 to VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1. Each
VID input offers a 20µA pull up to 2.5V for use with open-drain
outputs. External pull-up resistors or active-high output
stages can augment the pull-up current sources, but a slight
accuracy error can occur if they are pulled above 2.9V.
._{The DAC-selected reference voltage is connected to the non-}
inverting input of the error amplifier, and the output of the dif-
ferential remote-sense amplifier usually gets connected to
the error amplifier as shown in Figure 7. The remote-sense
amplifier eliminates voltage differences between local and
remote ground to provide a more accurate means of sensing
output voltage.
EXTERNAL CIRCUIT
R_C
C_C
COMP
ISL6557A INTERNAL CIRCUIT
FB
R_FB
+
V_DROOP
-
IOUT
VDIFF
ERROR AMPLIFIER
-
I_AVG
+
V_COMP
REFERENCE
VOLTAGE
V_OUT
VSEN
+
REMOTE
GROUND
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
The integrating compensation network shown in Figure 7
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the remote-sense and error
amplifiers. Intersil specifies the guaranteed tolerance of the
ISL6557A and all Intersil controllers to include all variations
in the amplifiers and reference so that the output voltage
remains within the specified system tolerance.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
VID3
VID2
VID1
VID0 VDAC
1
1
1
1
1
Off
1
1
1
1
0
0.800
1
1
1
0
1
0.825
1
1
1
0
0
0.850
1
1
0
1
1
0.875
1
1
0
1
0
0.900
1
1
0
0
1
0.925
1
1
0
0
0
0.950
1
0
1
1
1
0.975
1
0
1
1
0
1.000
1
0
1
0
1
1.025
1
0
1
0
0
1.050
1
0
0
1
1
1.075
1
0
0
1
0
1.100
1
0
0
0
1
1.125
1
0
0
0
0
1.150
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