ISL6557A Datasheet, PDF (13/19 Pages) Intersil Corporation – Multi-Phase PWM Controller for Core-Voltage Regulation

ISL6557A
dependent on the switching frequency (f_S), the size of the
change (∆V_ID), and the time before the next switching cycle
begins. The one-cycle uncertainty in Equation 9 is due to the
possibility that the VID code change may occur up to one full
cycle before being recognized. The time required for a
converter running with f_S = 500kHz to make a 1.3V to 1.5V
reference-voltage change is between 30µs and 32µs as
calculated using Equation 9. This example is also illustrated
in Figure 11.
--¹--
f_S


-²---^∆----^V----^I--^D--
0.025
–
1_
<
t_DV
≤
--¹--
f_S



-²---^∆----^V----^I--^D--
0.025 _
(EQ. 9)
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted on
either side; and the total board space available for power-
supply circuitry. Generally speaking, the most economical
solutions will be for each phase to handle between 15 and
20A. All-surface-mount designs will tend toward the lower
end of this current range and, if through-hole MOSFETs can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 30A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r_DS(ON)). In Equation 10, I_M is the maximum
continuous output current; I_L,PP is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (V_OUT/V_IN); and
L is the per-channel inductance.
P _{L O W ,1}
=
r_DS(ON)



-^I-^M---
N
2
(
1
–
d
)
+
I_{--L----,-P----P2----}(_--1_{-----–-----}d_----)
12
(EQ. 10)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON); the switching frequency,
f_S; and the length of dead times, t_d1 and t_d2, at the
beginning and the end of the lower-MOSFET conduction
interval respectively.
P_{LOW, 2}
=
V_D(ON) f_S


-^I-^M---
N
+
I_{--P-2---P--}
t_d1
+



I_--M---
N
–
I_{--P--2--P--}
t_d2
(EQ. 11)
Thus the total power dissipated in each lower MOSFET is
approximated by the summation of P_L and P_D.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V_IN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependant
on switching frequency, the power calculation is somewhat
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q_rr; and the upper MOSFET r_DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 12,
the required time for this commutation is t₁and the
associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN



I_--M---
N
+
-^I-^L----^,-^P----^P--
2



t_--1--
2



f_S
(EQ. 12)
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. In Equation 13, this transition occurs
over a time t₂, and the approximate the power loss is P_UP,2.
P_{UP, 2}
≈
V_IN


I_--M---
N
–
-^I-^L----^,-^P----^P--
2



t_--2--


2_
f_S
(EQ. 13)
A third component involves the lower MOSFET’s reverse-
recovery charge, Q_rr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can recover all of Q_rr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P_UP,3 and is simply
P_UP,3 = V_IN Q_rr f_S
(EQ. 14)
13