ISL6557A Datasheet, PDF (12/19 Pages) Intersil Corporation – Multi-Phase PWM Controller for Core-Voltage Regulation

ISL6557A
During the soft-start interval, the soft-start voltage, V_RAMP,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I_RAMP, is
decreasing from 160µA down to zero. These signals are
connected as shown in Figure 9 (I_OUT may or may not be
connected to FB depending on the particular application).
EXTERNAL CIRCUIT
R_C
C_C
COMP
ISL6557A INTERNAL CIRCUIT
ERROR AMPLIFIER
FB
-
R_FB
IOUT
VDIFF
+
V_COMP
I_RAMP
REFERENCE
VOLTAGE
I_AVG
V_RAMP
IDEAL DIODES
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
The ideal diodes in Figure 9 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V_RAMP. Since I_RAMP creates an initial offset
across R_FB of R_FB times 160µA, the first PWM pulses will
not be seen until V_RAMP is greater than the R_FB I_RAMP
offset. This produces a delay after the ISL6557A enables
before the output voltage starts moving. For example, if
VID = 1.5V, R_FB = 1kΩ and T_SS = 8.3ms, the delay time
can be expressed using Equation 6.
t_DELAY = -₁----+------_R---------_{F--------1B---}^T---_.--1--4^S_----6----(^S_{--0----V------×--I----D----1----)--0--------–------6--} = 580µs
(EQ. 6)
From this point, the soft start ramps linearly until V_RAMP
reaches VID. For the system described above, this first linear
ramp will continue for approximately
t_RAMP1
=
T_{----S----S-- –}
1.4
t_DELAY
= 5.27ms
(EQ. 7)
The final portion of the soft-start sequence is the time
remaining after V_RAMP reaches VID and before I_RAMP gets to
zero. This is also characterized by a slight linear ramp in the
output voltage which, for the current example, exists for a time
t_RAMP2 = T_SS – t_RAMP1 – t_DELAY
= 2.34ms
(EQ. 8)
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, R_FB is set to 2.67kΩ
leading to T_SS = 4.0ms, t_DELAY = 700ns, t_RAMP1 = 2.23ms,
and t_RAMP2 = 1.17ms.
VOUT, 500mV/DIV
EN, 5V/DIV
t_DELAY t_RAMP1 t_RAMP2 ^1ms/DIV
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6557A
BASED MULTI-PHASE BUCK CONVERTER
NOTE: Switching frequency 500kHz and R_FB = 2.67kΩ
DYNAMIC VID
The ISL6557A is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation), the
ISL6557A checks for a change in the VID code. The VID
code is the bit pattern present at pins VID4-VID0 as outlined
in Voltage Regulation. If the new code remains stable for
another full cycle, the ISL6557A begins incrementing the
reference by making 25mV change every two switching
cycles until the it reaches the new VID code.
01110
00010
V_ID, 5V/DIV
VID CHANGE OCCURS
ANYWHERE HERE
1.3V
V_REF, 100mV/DIV
1.3V
V_OUT, 100mV/DIV
5µs/DIV
FIGURE 11. DYNAMIC-VID WAVEFORMS FOR 500KHZ
ISL6557A BASED MULTI-PHASE BUCK
CONVERTER
Since the ISL6557A recognizes VID-code changes only at
the beginnings of switching cycles, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
Thus, the total time required for a VID change, t_DV, is
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