ISL6550A Datasheet, PDF (9/11 Pages) Intersil Corporation – SAM Supervisor And Monitor

ISL6550A, ISL6550C
Applications Information
Here are some step-by-step guidelines to help set up a
circuit. Use the block diagram for reference.
1. Use a 12V (±10%) Power Supply; connect to VCC and
GND. Connect a 0.1µF bypass capacitor across the pins.
2. Determine the minimum and maximum DAC values
required. VREF5 is a precision 5V buffered output;
connect R1, R2, R3 as a divider, to select the upper and
lower range for the DAC. A total of 50kΩ for the 3
resistors is recommended. The maximum for DACHI is
5.0V; the minimum for DACLO is 0.8V. The difference
between DACHI and DACLO, divided by 31, determines
the step size of the DAC.
DACLO = (5V) * (R3)/(R1 + R2 + R3)
DACHI = (5V) * (R3 + R2)/(R1 + R2 + R3)
STEP = (DACHI - DACLO) / 31
For example, if R1 is 24K, R2 is 16K, and R3 is 10K,
then DACLO = 1.0V, DACHI = 2.6V, and STEP = 0.05V
3. Within the above range, select the VID code for the
desired BDAC output voltage. (This is typically used as a
reference for a DC/DC converter system). Connect the
VID bits accordingly (GND is a logic low; open/floating or
2V and above is a logic high).
4. Now that BDAC is set up as the desired reference
voltage, the next step is to decide how far from this
voltage the system voltage (typically the DC/DC
converter output) is allowed to go, before shutting down
the system. Select R4 and R5 to create the Undervoltage
threshold. R4 + R5 should total around 50kΩ, so as not to
load the BDAC.
OVUVTH = BDAC * (R5) / (R4 + R5).
The threshold is a percentage of whatever the BDAC
voltage is. If we define delta = (BDAC - OVUVTH), then
the SAM will take that voltage, and mirror it up, to create
an internal Overvoltage trip point of BDAC + delta, which
is the same voltage above the BDAC that the UV trip point
is below BDAC (the trip points are symmetrical by design).
For example, if BDAC is 2.5V, R5 is 40K, and R4 is 10K,
then OVUVTH = 2.0V. Since the UV threshold is 0.5V
below BDAC, the internal OV threshold will be 0.5V above
BDAC, or 3.0V. So, if during normal operation, the
converter output voltage is pulled past either trip point, the
START and PGOOD signals will change state, and can be
used to shut down the converter. Note that there is also
hysteresis for both trip points; it varies with each logic
option; see Logic Options Table.
If an opamp is needed to help condition or filter the input
signal at OVUVSEN, the spare one can be used. It can
also be used to change the gain, if the voltage to be
compared is not equal to the BDAC voltage. And if the
opamp is not needed here, it can still be used for any
other purpose.
There is an optional Undervoltage Delay circuit. This
allows the system to ignore an excursion below the UV
trip point for a short time period (for example, during a
power-up sequence). When the UV trip point is
exceeded, an external capacitor (C1 to GND) on the
UVDLY pin gets charged through an internal 20µA
current source. If the OVUVSEN input is still below the
trip point when the UVDLY pin reaches a nominal 5V, it
will make the internal UVD signal a logic high, and the
START or PGOOD will react accordingly.
The delay time dt uses the formula I = C * dv/dt. In this
case, dt = C1 * 5V/20µA. Or solve for C1 = (20µA) *
(dt)/5V. Practical values for C range from 100pF (for
25µs) up to 0.1µF (for 25ms).
5. There is an UVLO (Undervoltage Lock-Out); also called
POR (Power-On-Reset), so as not to be confused with
the Undervoltage detection. This block monitors the VDD
voltage; it releases around 9.4V as the power supply
turns on, and has about 1.0V of hysteresis. This block
only affects the START and PGOOD outputs.
6. The Logic block takes the various input and internal
conditions (PEN, UV, OV, UVDLY, POR), and combines
them logically to create the START and PGOOD outputs.
These pins require some kind of external pull-up resistor
(or equivalent); the pull-ups can be to the 12V supply, or
any lower voltage compatible with the external logic. The
value of the resistors depend on the pull-up voltage, the
current desired, the logic voltage levels, rise or fall time
considerations, etc.; A typical value would be 5kΩ. The
FAULT latch is set by a combination of input conditions; it
is reset by POR or PEN (see Logic Options).
The advantage of the latch is that a momentary fault can
be saved, and the user must do something (power down
or toggle PEN) to recover. But some users might call that
same scenario a disadvantage. So there are two
different logic options to choose from. Which one is
best? Which logic signals should you use?
It depends upon what’s available in the system. The
PEN input is useful, for example, because it can reset
the FAULT latch of the C version; the A version requires
the user to power down to reset. But does the system
have a signal available to do that function? So part of the
choice among the logic options is whether the system is
smart enough to diagnose and correct a problem, or
does it just shut everything down, and wait for help.
9
FN9036.4
January 18, 2005