ISL6550A Datasheet, PDF (4/11 Pages) Intersil Corporation – SAM Supervisor And Monitor

ISL6550A, ISL6550C
Pin Descriptions
NOTE: Pin numbers refer to the 20 lead SOIC package. Please
check PINOUT diagrams for QFN pin numbers.
VCC (Positive Supply Voltage) Pin 1 - This power pin
supplies power to the IC; nominally 12V. It should be
bypassed directly to the GND pin with a 0.1µF low ESR/ESL
capacitor.
GND (Signal Ground) Pin 6 - This power pin is the
reference ground connection for the IC, and any circuitry that
provides input/output to/from it.
VID0-VID4 (DAC Digital Input Code Control) Pins 15-11 -
These are the DAC digital input control code lines. VID0
represents the least significant bit (LSB) and VID4
represents the most significant bit (MSB). Table 1 shows all
of the codes, and their results. Note that setting all input
codes low produces the maximum voltage at BDAC. The
minimum voltage results when all codes are set high. Logic
zero is considered system ground. A floated input or an input
held higher than 2.0V is considered a logic one level. An
internal 10µA current source pulls open VID pins to a logic
high (nominal 1.6V). The pins are also TTL and LVTTL
compatible.
PEN (Power Supply Enable) Pin 18 - This digital input pin
enables the external converter through the START or
PGOOD pins. A logic high (or float) enables the output
voltage, and a logic low disables it. This pin has a 10µA pull-
up current source, so it can interface with an open-collector
or open-drain driver. When disabled, the START output is
low and the PGOOD output is low.
OVUVTH (Overvoltage/Undervoltage THreshold) Pin 8 -
This analog input pin is used to program the window
thresholds for the OV and UV comparators. The OV-UV
window is centered around the BDAC voltage and can be
programmed from ±5% to ±40% about the BDAC voltage.
This pin’s voltage sets the undervoltage threshold. Internal
circuitry sets the overvoltage threshold such that the two
thresholds are centered about BDAC, the DAC output
voltage. For example, if BDAC is 2.5V, and OVUVTH is 2.0V
(0.5V below BDAC), then the internal OV threshold is 3.0V
(0.5V above BDAC).
OVUVSEN (Overvoltage/Undervoltage SENse) Pin 19 -
This analog input pin is the sense voltage for Undervoltage
and Overvoltage purposes. A resistor divider from the BDAC
output sets the UV level, on the OVTH/UVTH pin; the IC will
internally mirror a similar voltage for OV, and then compare
them both to the OVUVSEN input.
DACHI (HIgh Limit of BDAC Voltage Range) Pin 9 - This
analog input pin sets the high level of the BDAC, and is
programmed through the external 3-resistor divider (R1, R2,
R3) shown in the block diagram.
DACLO (LOw Limit of BDAC Voltage Range) Pin 10 -
This analog input pin sets the low level of the BDAC, and is
programmed through the external 3-resistor divider shown in
the block diagram.
NOTE: A total resistance of around 50K is optimal for R1, R2, and
R3. Adjust the ratios of these resistors to get the desired DACHI and
DACLO voltage levels.
UVDLY (Under Voltage Delay) Pin 20 - This is an analog
input/output pin. When the Undervoltage threshold is
exceeded, a potential fault is detected. A capacitor tied to
the UVDLY pin is charged by an internal 10µA source. The
ramp time of the capacitor to the threshold voltage (5V
nominal) determines the delay. (no capacitor gives
essentially no delay).
VOPP (Positive Opamp Input) Pin 2 - This analog input pin
is the positive input of the Opamp.
VOPM (Minus Opamp Input) Pin 3 - This analog input pin
is the minus input of the Opamp.
VOPOUT (Opamp Output) Pin 4 - This analog output pin is
the output of the Opamp.
BDAC (Buffered Digital-to-Analog Converter) Pin 7 - This
analog output pin is the output of the 5-bit DAC. Setting all
input codes low produces the maximum voltage at BDAC.
The minimum voltage results when all codes are set high.
See Table 1 for codes.
VREF5 (5V Reference Voltage) Pin 5 - This is an analog
output pin, which provides a precision reference voltage for
setting DACHI and DACLO voltage levels.
START Pin 17 - This is an open-drain pull-down digital
output pin; it is pulled low when one or more of the monitored
conditions is not valid; the output goes high impedance (to
be pulled high externally through a pull-up resistor or
equivalent) if all conditions are met. See Logic Options Table
for the various conditions.
PGOOD (Power Good) Pin 18 - This is an open-drain pull-
down digital output pin; it is pulled low when one or more of
the monitored conditions is not valid; the output goes high
impedance (to be pulled high externally through a pull-up
resistor or equivalent)) if all conditions are met. See Logic
Options Table for the various conditions.
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FN9036.4
January 18, 2005