ISL6550A Datasheet, PDF (3/11 Pages) Intersil Corporation – SAM Supervisor And Monitor

Block Diagram
VOPM 3
VOPP ₂
VOPOUT 4
PEN 16
OPAMP
-
+
10µA TO 5V
ISL6550A, ISL6550C
VREF5
5
VCC
1
BUFFERED
5V
5V REF
LOGIC BLOCK
SEE OPTIONS A, C BELOW
ST
PEN: H = ENABLE; L = DISABLE
OVUVSEN 19
OVUVTH 8
THRESHOLD
PROGRAM
R1
UVLOCKOUT
(POR)
OV
UV
UV/OV HYST:
SEE NOTE
BELOW
POR: H = VDD TOO LOW; L = VDD OK
OV: H = OVERVOLTAGE; L = OK
UV: H = UNDERVOLTAGE; L = OK
PG
UVD: H = UV DELAY TIMED OUT;
L = NO TIME-OUT
DACHI 9
(EACH VID PIN)
VID4 ₁₁
10µA TO 5V
VID3 12
VID2 13
VID1 14
R2
VID0 15
5-BIT
DAC
UVDELAY
DAC _BUFFER
DACLO 10
R3
6
GND
NOTE: Pin numbers shown are for the 20 lead SOIC package. Please check PINOUT diagrams for QFN pin numbers.
A
PEN
POR
NOTE: UV/OV
Q
Hysteresis = 10%
ST
POR
OV
UV
UVD
PEN
R
Q ^{Q: H = FAULT;}
L = NO FAULT
S
FAULT
LATCH
PEN
POR
Q
PG
UV
NOTE: S input dominates Q
C
PEN
POR
NOTE: UV/OV
Hysteresis = 10%
Q
ST
POR
PEN
OV
UV
UVD
PEN
R
Q ^{Q: H = FAULT;}
L = NO FAULT
S
FAULT
LATCH
POR
OV
UV
PG
NOTE: S input dominates Q
R_ST
17 START
R_PG
18 PGOOD
20 ^UVDLY
(OPT)
C1
7 BDAC
R4
R5
3
FN9036.4
January 18, 2005