ISL62870 Datasheet, PDF (9/16 Pages) Intersil Corporation – PWM DC/DC Voltage Regulator Controller

ISL62870
output voltage (V_OUT) at the VO pin. The positive slope of
V_R can be written as Equation 10:
V_RPOS = (g_m) ⋅ (V_IN – V_OUT) ⁄ C_R
(EQ. 10)
The negative slope of V_R can be written as Equation 11:
V_RNEG = g_m ⋅ V_OUT ⁄ C_R
(EQ. 11)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is controlled internally by the IC. The V_R, V_COMP, and
V_W signals feed into a window comparator in which V_COMP
is the lower threshold voltage and V_W is the higher threshold
voltage. Figure 6 shows PWM pulses being generated as V_R
traverses the V_W and V_COMP thresholds. The PWM
switching frequency is proportional to the slew rates of the
positive and negative slopes of V_R; it is inversely
proportional to the voltage between V_W and V_COMP.
RIPPLE CAPACITOR VOLTAGE C_R
WINDOW VOLTAGE V_W
ERROR AMPLIFIER VOLTAGE V_COMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction through
the output inductor when the high-side MOSFET switches off
for the balance of the PWM switching cycle. Low conversion
efficiency as a result of the conduction loss of the diode
makes this an unattractive option for all but the lowest
current applications. Efficiency is dramatically improved
when the free-wheeling diode is replaced with a MOSFET
that is turned on whenever the high-side MOSFET is turned
off. This modification to the standard DC/DC buck regulator
is referred to as synchronous rectification, the topology
implemented by the ISL62870 controller.
Diode Emulation
The polarity of the output inductor current is defined as positive
when conducting away from the phase node, and defined as
negative when conducting towards the phase node. The DC
component of the inductor current is positive, but the AC
component known as the ripple current, can be either positive
or negative. Should the sum of the AC and DC components of
the inductor current remain positive for the entire switching
period, the converter is in continuous-conduction-mode (CCM.)
However, if the inductor current becomes negative or zero, the
converter is in discontinuous-conduction-mode (DCM.)
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL62870 controller avoids the DCM conduction
loss by making the low-side MOSFET emulate the current
blocking behavior of a diode. This smart-diode operation
called diode-emulation-mode (DEM) is triggered when the
negative inductor current produces a positive voltage drop
across the r_DS(ON) of the low-side MOSFET for eight
consecutive PWM cycles while the LGATE pin is high. The
converter will exit DEM on the next PWM pulse after
detecting a negative voltage across the r_DS(ON) of the low-
side MOSFET.
It is characteristic of the R³ architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the
PWM frequency is forced to fall approximately 30% by
forcing a similar increase of the window voltage V_W. This
measure is taken to prevent oscillating between modes at
the boundary between CCM and DCM. The 30% increase of
V_W is removed upon exit of DEM, forcing the PWM switching
frequency to jump back to the nominal CCM value.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) threshold
voltage V_{VCC_THR}. The controller will become disabled
when the voltage at the VCC pin decreases below the falling
POR threshold voltage V_{VCC_THF}. The POR detector has a
noise filter of approximately 1µs.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the V_ENTHR rising threshold
voltage, the following criteria must be met:
1. V_PVCC is at least equivalent to the VCC rising power-on
reset voltage V_{VCC_THR}
2. V_VIN must be 3.3V or the minimum required by the
application.
Start-Up Timing
Once VCC has ramped above V_{VCC_THR}, the controller can
be enabled by pulling the EN pin voltage above the input high
threshold V_ENTHR. Approximately 20µs later, the voltage at the
SREF pin begins slewing to the designated VID set-point. The
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FN6708.0
August 14, 2008