ISL62870 Datasheet, PDF (8/16 Pages) Intersil Corporation – PWM DC/DC Voltage Regulator Controller

ISL62870
For example, if I_OC is 20A and DCR is 4.5mΩ, the choice of
R_OCSET is = 20Ax4.5mΩ/10µA = 9kΩ.
Resistor R_OCSET and capacitor C_SEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R_OCSET C_SEN
needs to match the inductor time constant L/DCR. The value
of C_SEN is then written as follows:
C_SEN
=
--------------------^L----------------------
R_OCSET ⋅ DCR
(EQ. 9)
For example, if L is 1.5µH, DCR is 4.5mΩ, and R_OCSET is
9kΩ, the choice of C_SEN = 1.5µH/(9kΩx4.5mΩ) = 0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V_ENTHF or if VCC has decayed
below the falling POR threshold voltage ^V_{VCC_THF}
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold V_OVRTH for
more than 2µs. For example, if the converter is programmed
to regulate 1.0V at the FB pin, that voltage would have to
rise above the typical V_OVRTH threshold of 116% for more
than 2µs in order to trip the OVP fault latch. In numerical terms,
that would be 116% x 1.0V = 1.16V. When an OVP fault is
declared, the PGOOD pin will pull-down to 65Ω and latch-off
the converter. The OVP fault will remain latched until VCC
has decayed below the falling POR threshold voltage
V_{VCC_THF. An OVP fault cannot be reset by pulling the EN}
pin below the falling EN threshold voltage V_ENTHF.
Although the converter has latched-off in response to an OVP
fault, the LGATE gate-driver output will retain the ability to
toggle the low-side MOSFET on and off, in response to the
output voltage transversing the V_OVRTH and V_OVFTH
thresholds. The LGATE gate-driver will turn-on the low-side
MOSFET to discharge the output voltage, protecting the load.
The LGATE gate-driver will turn-off the low-side MOSFET
once the FB pin voltage is lower than the falling overvoltage
threshold V_OVRTH for more than 2µs. The falling overvoltage
threshold V_OVFTH is typically 102%. That means if the FB pin
voltage falls below 102% x 1.0V = 1.02V, for more than 2µs,
the LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the LGATE driver will again
turn on the low-side MOSFET when the FB pin voltage is
above the rising overvoltage threshold V_OVRTH for more than
2µs. By doing so, the IC protects the load when there is a
consistent overvoltage condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V_UVTH for more
than 2µs. For example, if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
below the typical V_UVTH threshold of 84% for more than 2µs
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. When a UVP fault is declared,
the PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage V_ENTHF
or if VCC has decayed below the falling POR threshold
voltage ^V_{VCC_THF}.
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature T_OTRTH, it will enter the OTP state
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T_OTHYS, at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V_ENTHF or if
VCC has decayed below the falling POR threshold voltage
V_{VCC_THF. All other protection circuits remain functional}
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
V_UVTH.
Theory of Operation
The modulator features Intersil’s R³ Robust-Ripple
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The PWM
frequency is maintained at 300kHz under static continuous
conduction mode operation within the entire specified
envelope of input voltage, output voltage, and output load. If
the application should experience a rising load transient
and/or a falling line transient such that the output voltage
starts to fall, the modulator will extend the on-time and/or
reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and duty cycle of the ensuing PWM
pulses are optimized by the R³ modulator for the remainder
of the transient and work in concert with the error amplifier
V_ERR to maintain output voltage regulation. Once the
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300kHz.
Modulator
The R³ modulator synthesizes an AC signal V_R, which is an
analog representation of the output inductor ripple current.
The duty-cycle of V_R is the result of charge and discharge
current through a ripple capacitor C_R. The current through
C_R is provided by a transconductance amplifier g_m that
measures the input voltage (V_IN) at the PHASE pin and
8
FN6708.0
August 14, 2008