ISL62870 Datasheet, PDF (10/16 Pages) Intersil Corporation – PWM DC/DC Voltage Regulator Controller

ISL62870
converter output voltage at the FB feedback pin follows the
voltage at the SREF pin. During soft-start, the regulator always
operates in CCM until the soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an undefined
impedance if the VCC pin has not reached the rising POR
threshold V_{VCC_THR}, or if the VCC pin is below the falling
POR threshold V_{VCC_THF}. The PGOOD pull-down resistance
corresponds to a specific protective fault, thereby reducing
troubleshooting time and effort. Table 1 maps the pull-down
resistance of the PGOOD pin to the corresponding fault status
of the controller.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft-Start or Undervoltage
95Ω
Overvoltage
65Ω
Overcurrent
35Ω
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of the
converter while the UGATE pin drives the high-side
MOSFET of the converter.
The LGATE driver is optimized for low duty-cycle
applications where the low-side MOSFET experiences long
conduction times. In this environment, the low-side
MOSFETs require exceptionally low r_DS(ON) and tend to
have large parasitic charges that conduct transient currents
within the devices in response to high dv/dt switching
present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver
pull-down resistance that the V_GS(th) of the device can be
exceeded and turned on. For this reason, the LGATE driver
has been designed with low pull-down resistance and high
sink current capability to ensure clamping the MOSFETs
gate voltage below V_GS(th).
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V. The dead-time shown in
Figure 7 is extended by the additional period that the falling
gate voltage remains above the 1V threshold. The high-side
gate-driver output voltage is measured across the UGATE
and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is supplied
by a boot-strap capacitor connected across the BOOT and
PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop below PVCC, such as when
the low-side MOSFET is turned on.
UGATE
1V
1V
1V
1V
LGATE
FIGURE 7. GATE DRIVER ADAPTIVE SHOOT-THROUGH
Compensation Design
Figure 8 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C_INT is a 100pF capacitor
integrated inside the IC, connecting across the FB pin and the
COMP signal. R_FB, R_COMP, C_COMP and C_INT form the Type-II
compensator. The frequency domain transfer function is given
by Equation 12:
G_COMP(s) = -_s----_â‹---_R-----¹_F---_B-+----_â‹-^s--_C---^â‹--_I-⁽-_N-^R---_T--^F---_â‹^B---₍--₁^+-----+R-----_s^C----^O_â‹---_R--^M---_C-^P---_O-⁾---_M-^â‹---^C-_P---^C--_â‹--^O-_C----^M-_C----^PO----_M-----_P-----₎ (EQ. 12)
C_INT = 100pF
R_COMP
C_COMP
COMP
-
FB
EA
+
SREF
R_FB
R_OFS
VOUT
FIGURE 8. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R³ modulator used in the
IC makes the LC output filter resemble a first order system in
which the closed loop stability can be achieved with the
recommended Type-II compensation network. Intersil provides
a PC-based tool that can be used to calculate compensation
network component values and help simulate the loop
frequency response.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
10
FN6708.0
August 14, 2008