ISL62870 Datasheet, PDF (12/16 Pages) Intersil Corporation – PWM DC/DC Voltage Regulator Controller

ISL62870
we select a capacitor with at least a breakdown rating of 10V.
The bootstrap capacitor can be chosen from Equation 20:
C_B
OOT
≥
---^Q----^G-----^A----^T---^E----
ΔV_BOOT
(EQ. 20)
Where:
- Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET
- ΔV_BOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor such as X7R or X5R is
recommended.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function
of the switching frequency and total gate charge of the
selected MOSFETs. Calculating the power dissipation in the
driver for a desired application is critical to ensuring safe
operation. Exceeding the maximum allowable power
dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C.
When designing the application, it is recommended that the
following calculation be performed to ensure safe operation
at the desired frequency for the selected MOSFETs. The
power dissipated by the drivers is approximated using
Equation 21:
P = F_sw(1.5V_UQ_U + V_LQ_L) + P_L + P_U
(EQ. 21)
Where:
- F_sw is the switching frequency of the PWM signal
- V_U is the upper gate driver bias supply voltage
- V_L is the lower gate driver bias supply voltage
- Q_U is the charge to be delivered by the upper driver into
the gate of the MOSFET and discrete capacitors
- Q_L is the charge to be delivered by the lower driver into
the gate of the MOSFET and discrete capacitors
- P_L is the quiescent power consumption of the lower driver
- P_U is the quiescent power consumption of the upper driver
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V_DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
1000
900
800
Q_U = 100nC
Q_L = 200nC
Q_U = 50nC
Q_L = 100nC
Q_U = 50nC
Q_L= 50nC
700
600
Q_U = 20nC
Q_L= 50nC
500
400
300
200
100
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
FIGURE 11. POWER DISSIPATION vs FREQUENCY
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET,
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
V_IN - V_OUT, plus the spike, across it. The preferred low-side
MOSFET emphasizes low r _DS(ON) when fully saturated to
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as Equation 22:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} ⋅ (1 – D)
(EQ. 22)
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 23:
P_{CON_HS}
=
I_L
O
A
2
D
⋅
r_D
S
(ON)_H
S
⋅
D
(EQ. 23)
For the high-side MOSFET, its switching loss is written as
Equation 24:
P_{SW_HS}
=
V_{-----I--N-----}⋅_---I_{--V----A----L---L---E----Y-----}⋅_---t_{--O-----N-----}⋅_---F_{----S----W---}
2
+
-^V----^I--^N-----^â‹---^I--^P----^E----^A----^K-----^â‹---^t-^O-----^F----^F----^â‹---^F----^S----^W---
2
(EQ. 24)
12
FN6708.0
August 14, 2008