ISL6269B_14 Datasheet, PDF (9/16 Pages) Intersil Corporation – High-Performance Notebook PWM Controller With Audio-Frequency Clamp

ISL6269B
Theory of Operation
Modulator
The ISL6269B is a hybrid of fixed frequency PWM control and
variable frequency hysteretic control. Intersil’s R3™ Technology can
simultaneously affect the PWM switching frequency and PWM duty
cycle in response to input voltage and output load transients. The
term “Ripple” in the name “Robust Ripple Regulator” refers to the
converter output inductor ripple current, not the converter output
ripple voltage. The R3™ Modulator synthesizes an AC signal V_R,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of V_R is the result of charge and discharge
current through a ripple capacitor C_R. The current through C_R is
provided by a transconductance amplifier g_m that measures the VIN
and VO pin voltages. The positive slope of V_R can be written as:
V_RPOS = g_m  V_IN – V_OUT
(EQ. 1)
The negative slope of V_R can be written as:
V_RNEG = g_m  V_OUT
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into which
the ripple voltage V_R is compared. The amplitude of V_W is set by
a resistor connected across the FSET and GND pins. The V_R,
V_COMP and V_W signals feed into a window comparator in which
V_COMP is the lower threshold voltage and V_W is the higher
threshold voltage. Figure 1 shows PWM pulses being generated
as V_R traverses the V_W and V_COMP thresholds. The PWM
switching frequency is proportional to the slew rates of the
positive and negative slopes of V_R; the PWM switching frequency
is inversely proportional to the voltage between V_W and V_COMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
EN, Soft-Start and PGOOD
The ISL6269B uses a digital soft-start circuit to ramp the output
voltage of the converter to the programmed regulation setpoint
at a predictable slew rate. The slew rate of the soft-start
sequence has been selected to limit the in-rush current through
the output capacitors as they charge to the desired regulation
voltage. When the EN pin is pulled above the rising EN threshold
voltage V_ENTHR the PGOOD soft-start delay t_SS begins and the
output voltage begins to rise. The output voltage enters regulation
in approximately 1.5ms and the PGOOD pin goes to high
impedance once t_SS has elapsed.
1.5ms
VOUT
VCC and PVCC
EN
PGOOD
2.75ms
FIGURE 2. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an undefined
impedance if V_VCC has not reached the rising POR threshold
V_{VCC_THR}, or if V_VCC is below the falling POR threshold V_{VCC_THF}.
The ISL6269B features a unique fault-identification capability
that can drastically reduce troubleshooting time and effort. The
pull-down resistance of the PGOOD pin corresponds to the fault
status of the controller. During soft-start or if an undervoltage
fault occurs, the PGOOD pull-down resistance is 95Ω, or 30Ω for
an overcurrent fault, or 60Ω for an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
V_CC Below POR
Soft-start or Undervoltage
Undefined
95Ω
Overvoltage
60Ω
Overcurrent
30Ω
FIGURE 1. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
Power-On Reset
The ISL6269B is disabled until the voltage V_VCC has increased
above the rising power-on reset (POR) V_{VCC_THR} threshold voltage.
The controller will become once again disabled when the voltage
V_VCC decreases below the falling POR V_{VCC_THF} threshold voltage.
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FN6280.3
November 17, 2014