ISL6210 Datasheet, PDF (9/10 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6210
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and the power devices
(both upper and lower FETs) could cause serious ringing,
exceeding absolute maximum rating of the devices. The
negative ringing at the edges of the PHASE node could add
charges to the bootstrap capacitor through the internal
bootstrap diode, in some cases, it could cause over stress
across BOOT and PHASE pins. Therefore, user should do a
careful layout and select proper MOSFETs and drivers. The
D²PAK and DPAK package MOSFETs have high parasitic
lead inductance, which can exacerbate this issue. FET
selection plays an important role in reducing PHASE ring. If
higher inductance FETs must be used, a Schottky diode is
recommended across the lower MOSFET to clamp negative
PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
• Avoid uses via for decoupling components across BOOT
and PHASE pins and in between VCC and GND pins. The
decoupling loop should be short.
• All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using via; otherwise,
use two vias for interconnection when possible.
• Keep SOURCE of upper FET and DRAIN of lower FET as
close as thermally possible.
• Keep connection in between SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN
of upper FET and SOURCE of lower FETs as thermally
possible.
NOTE: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias is
recommended. This heat spreading allows the part to
achieve its full thermal potential.
9
FN6392.0
November 28, 2006