ISL6210 Datasheet, PDF (5/10 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6210
Electrical Specifications These specifications apply for T_A = -10°C to +100°C, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
UGATE Turn-On Propagation Delay
t_PDHU
V_VCC = 5V, Outputs Unloaded; R_SET = 80kΩ
-
41
-
LGATE Turn-On Propagation Delay
t_PDHL
V_VCC = 5V, Outputs Unloaded; R_SET = 80kΩ
-
33
-
Minimum LGATE On Time in DCM (Note 3)
t_LGMIN
-
400
-
OUTPUT
Upper Drive Source Resistance (Note 3)
Upper Drive Source Current (Note 3)
Upper Drive Sink Resistance (Note 3)
Upper Drive Sink Current (Note 3)
Lower Drive Source Resistance (Note 3)
Lower Drive Source Current (Note 3)
Lower Drive Sink Resistance (Note 3)
Lower Drive Sink Current (Note 3)
NOTE:
R_{UG_SRC}
I_{UG_SCR}
R_{UG_SNK}
I_{UG_SNK}
R_{LG_SRC}
I_{LG_SCR}
R_{LG_SNK}
I_{LG_SNK}
250mA Source Current
V_UGATE-PHASE = 2.5V
250mA Sink Current
V_UGATE-PHASE = 2.5V
250mA Source Current
V_LGATE = 2.5V
250mA Sink Current
V_LGATE = 2.5V
-
1.0
2.5
-
2.00
-
-
1.0
2.5
2.00
-
-
1.0
2.5
-
2.00
-
-
0.4
1.0
-
4.00
-
3. Guaranteed by Characterization. Not 100% tested in production.
UNITS
ns
ns
ns
Ω
A
Ω
A
Ω
A
Ω
A
Functional Pin Description
NUMBER NAME
FUNCTION
1
GND Bias and reference ground. All signals are referenced to this node.
2
LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
3
PVCC This pin supplies power to both the lower and higher gate drives in ISL6614. Its operating range is +5V to 12V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
4
FCCM Logic control input that will force continuous conduction mode (HIGH state) or allow discontinuous conduction mode
(LOW state). Placing a series resistor in this input will allow the switching dead-time to be programmed.
5
PGND It is the power ground return of both low gate drivers.
6
LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
7
EN Logic control input that will enable (HIGH state) or disable (LOW state) the IC. Shutdown current is <1μA.
8
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This pin
provides a return path for the upper gate drive.
9
UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this pin and
the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this pin and
the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13
PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This pin
provides a return path for the upper gate drive.
14
VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
15
PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.
16
PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller.
N/A
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6392.0
November 28, 2006