ISL6210 Datasheet, PDF (7/10 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6210
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
In addition to gate threshold monitoring, a programmable
delay between MOSFET switching can be accomplished by
placing a resistor in series with the FCCM input. This delay
allows for maximum design flexibility over MOSFET
selection. The delay can be programmed from 5ns to 50ns
and is obtained from the absolute value of the current
flowing into the FCCM pin. If no resistor is used, the
minimum 5ns delay is selected. Gate threshold monitoring is
not affected by the addition or removal of the additional
dead-time. Refer to Figure 2 and Figure 3 for more detail.
FCCM = VCC or GND
GATE A
GATE B
ADAPTIVE SHOOT-THROUGH
PROTECTION
1V
GATE A
FCCM = RESISTOR to VCC or GND
GATE B
ADAPTIVE PROTECTION
WITH DELAY
T_DELAY = 5n - 50ns
1V
FIGURE 2. PROGRAMMABLE DEAD-TIME
50
45
40
35
30
t_DELAY
25
20
15
10
5
0
0
167
333
500
667
833
1000
R_DELAY (kΩ)
FIGURE 3. ISL6210 PROGRAMMABLE DEAD-TIME vs
DELAY RESISTOR
The equation governing the dead-time seen in Figure 3 is
expressed as:
T_DELAY(ns) = [0.045 × R_DELAY(kΩ)] + 5ns
(EQ. 1)
The equation can be rewritten to solve for R_DELAY as
follows:
R_DELAY(kΩ)
=
(_---T_{----D----E----L---A----Y----(--n---s----)---–----}5_----n_----s_----)
0.045
(EQ. 2)
Internal Bootstrap Diode
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The following equation helps select a proper bootstrap
capacitor size:
C_B
O
O
T
_CAP
≥
----------^Q-----^G----^A----^T---^E-----------
Δ V_{B O O T _CAP}
(EQ. 3)
Q_GATE=
Q_{-----G-----1----}•_-----P_----V_-----C_----C_---
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q_G, from the data
sheet is 10nC at 4.5V (V_GS) gate-source voltage. Then the
Q_GATE is calculated to be 22nC at PVCC level. We will
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.110μF is required. The next larger standard value
7
FN6392.0
November 28, 2006