ISL55100A_14 Datasheet, PDF (9/14 Pages) Intersil Corporation – Quad 18V Pin Electronics Driver/Window Comparator

ISL55100A
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VEE pin is connected to ground,
one 0.1µF ceramic capacitor should be placed from the VCC
pin to ground. A 4.7µF tantalum capacitor should then be
connected from the VCC pin to ground. This same capacitor
combination should be placed at each supply pin to ground if
split supplies are to be used.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver level
amplitudes are key in determining power supply requirements
as well as dissipation/cooling necessities. Driver Output
patterns also impact these needs. The faster the pin activity,
the greater the need to supply current and remove heat.
Figures 17 and 18 address power consumption relative to
Frequency of Operation. These graphs are based on Driving
6.0/0.0V Out into a 1kΩ Load. T_jA for the device package is
23.0°C/W, 16.6°C/W and 14.9°C/W based on airflows of
0m/s, 1m/s and 2.5m/s. The device is mounted per Note 4
under “Thermal Information” on page 4. With the high speed
data rate capability of the ISL55100A, it is possible to exceed
the +150°C “absolute maximum junction temperature” as
operating conditions and frequencies increase. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if operating conditions need to be
modified for the device to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
P_DMAX
=
T_{----J---M-----A----X------}-_----T_{----A----M----A----X--}
_JA
(EQ. 1)
where:
• T_JMAX = Maximum junction temperature
• T_AMAX = Maximum ambient temperature
• _JA = Thermal resistance of the package
• P_DMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads. Power also
depends on the number of channels changing state, and the
frequency of operation. The extent of continuous active pattern
generation/reception will greatly effect dissipation
requirements.
The power dissipation curves (Figure 17), provide a way to see
if the device will overheat. The junction temperature rise above
ambient vs. operating frequency can be found graphically in
Figure 18. This graph is based on the package type T_JA ratings
and actual current/wattage requirements of the ISL55100A
when driving a 1k load with a 6V High Level and a 0V Low Rail.
The temperatures are indicated as calculated junction
temperature over the ambient temperature of the user’s
system. Plots indicate temperature change as operating
frequency increases (the graph assumes continuous
operation). The user should evaluate various heat sink/cooling
options in order to control the ambient temperature part of the
equation. This is especially true if the user’s applications
require continuous, high speed operation.
The reader is cautioned against assuming the same level of
thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted. Great care must be taken to ensure Die
Temperature does not exceed Absolute Maximum Thermal
Limits.
Important Note: The ISL55100A package metal pad (EP) is
used for heat sinking of the device. It is electrically connected
to the negative supply potential (V_EE). If VEE is tied to ground,
the thermal pad can be connected to ground. Otherwise, the
thermal pad (V_EE) must be isolated from other power planes.
Power Supply Sequencing
The ISL55100A references every supply with respect to V_EE.
Therefore apply V_EE, then V_CC followed by the VH, VL busses,
then the COMP High and Comp Low followed by the CVA and
CVB Supplies. Digital Inputs should be set with a differential
bias as soon as possible. In cases where V_EXT is being utilized
(V_EXT = V_EE + 5.5V), it should be powered up immediately after
V_CC. Basically, no pin should be biased above V_CC or below V_EE.
Data Rates
Please note that the Frequency (MHz) in Figures 17 and 18
contain two transitions within each period. A digital application
that requires a new test pattern every 50ns would be running
at a 20MHz Data Rate. Figure 19 reveals that a 100ns period,
10MHz in frequency parlance, results in two 50ns digital
patterns.
ESD Protection
Figure 6 is the block diagram depicting the ESD protection
networks. The DOUT-to-VH diode is the upper FET’s
drain-to-body diode.
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FN7486.3
December 4, 2014