ISL51002_14 Datasheet, PDF (9/33 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
Pin Descriptions
SYMBOL
R_IN0, 1, 2
G_IN0, 1, 2
B_IN0, 1, 2
VREF_RED,
VREF_GREEN,
VREF_BLUE
SOG_IN0, 1, 2
HSYNC_IN0, 1, 2
VSYNC_IN0, 1, 2
COAST_IN
CLAMP_IN
CLOCKINV_IN
FBC_IN
FBC_OUT
RESET
XTAL_IN
XTAL_OUT
XCLK_OUT
SADDR
SCL
SDA
EXTCLK_IN
R[9:0]
G[9:0]
B[9:0]
DATACLK
DATACLK
HS_OUT
HSYNC_OUT
VSYNC_OUT
DESCRIPTION
Analog inputs. Red channels. AC couple through 0.1µF. Do not connect if not used.
Analog inputs. Green channels. AC couple through 0.1µF. Do not connect if not used.
Analog inputs. Blue channels. AC couple through 0.1µF. Do not connect if not used.
Analog inputs. Reference voltage for ADCs. Tie to 1.8V reference voltage (V_A1.8 is acceptable if low noise). Decouple with
0.1µF capacitor to GND_A.
Analog inputs. Sync on Green. Connect to corresponding Green channel video source through a 0.01µF capacitor in
series with a 500Ω resistor.
Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's HSYNC source. For 5V
signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pFcapacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GND_D if not used.
Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's VSYNC source. For 5V
signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pF capacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GND_D if not used.
Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transitions on
the active channel’s HSYNC/SOG.
Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the
clamp DAC.
Digital 3.3V input. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during VSYNC to allow 2x
undersampling to sample odd and even pixels on sequential frames. Tie to D_GND if unused.
Digital 3.3V input.Connect to the Fast Blank signal of a SCART connector.
3.3V digital output. A delayed version of the FBC_IN signal, aligned with the digital pixel data.
Digital 3.3V input, active low, 70kΩ pull-up to V_D. Take low for at least 1µs and then high again to reset the ISL51002. This
pin is not necessary for normal use and may be tied directly to the V_D supply.
Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended
loading). Typical oscillation amplitude is 1.0V_P-P centered around 0.5V.
Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended
loading). Typical oscillation amplitude is 1.0V_P-P centered around 0.5V.
3.3V digital output. Buffered crystal clock output at f_XTAL or f_XTAL/2. May be used as system clock for other system
components.
Digital 3.3V input. Address = 0x98 (1001100x) when tied low.
Address = 0 x 9A (1001101x) when tied high.
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Digital 3.3V input. External clock input for AFE.
3.3V digital output. 10-bit Red channel pixel data.
3.3V digital output. 10-bit Green channel pixel data.
3.3V digital output. 10-bit Blue channel pixel data.
3.3V digital output. Data (pixel) clock output.
3.3V digital output. Inverse of DATACLK.
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is
always purely horizontal sync (without any composite sync signals)
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This
output will pass composite sync signals and Macrovision signals if present on HSYNC_IN or SOG_IN.
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the
disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
9
FN6164.3
February 29, 2012