ISL51002_14 Datasheet, PDF (32/33 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
START COMMAND
Signals the beginning of serial I/O
ISL51002 SERIAL BUS ADDRESS
R/W _{ISL51002 Serial Bus Address Write}
This is the 7-bit address of the ISL51002 on the 2-wire bus. The
1
0
0
1
1
0
A
0
(PIN 67)
address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. R/W = 0,
indicating next transaction will be a write.
ISL51002 Register Address Write
A7
A6
A5
A4
A3
A2
A1
A0
This sets the initial address of the ISL51002’s configuration
register for subsequent reading.
START COMMAND
Ends the previous transaction and starts a new one
ISL51002 SERIAL BUS
R/W _{ISL51002 Serial Bus Address Write}
This is the 7-bit address of the ISL51002 on the 2-wire bus. The
1
0
0
1
1
0
A
1
(PIN 67)
address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. R/W = 1,
indicating next transaction(s) will be a read.
D7
D6
SIGNALS
FROM THE
HOST
SDA BUS
SIGNALS
FROM THE
ISL51002
ISL51002 Register Data Read(s)
D5
D4
D3
D2
D1
D0
This is the data read from the ISL51002’s configuration register.
(REPEAT IF DESIRED)
Note: The ISL51002’s Configuration Register’s address pointer
auto increments after each data read: repeat this step to read
multiple sequential bytes of data from the Configuration Register.
STOP COMMAND
Signals the ending of serial I/O
S
T
A
SERIAL
BUS
R ^ADDRESS
T
REGISTER
ADDRESS
R
E
S
T
A
R
SERIAL BUS
ADDRESS
T
100110A0 aaaaaaaa 100110A1
DATA
READ*
S
T
O
AP
C
K
A
A
C
C
K
K
A
C
d
d
d
d
d
d
d
d
K
* The data read step may be repeated to read
from the ISL51002’s Configuration Register
sequentially, beginning at the Register
Address written in the two steps previous.
FIGURE 7. CONFIGURATION REGISTER READ
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web
to make sure you have the latest revision.
DATE
REVISION
CHANGE
November 17, 2011
FN6164.3
Added “Revision History” table.
Changed description of ISL51002's input multiplexer from 4 channels to 3 channels due to discovery of
significant signal leakage between channel 3 and channel 1 when channel 3 was selected. This is not a
silicon change - all ISL51002s have always had this issue; it was not discovered until recently.
32
FN6164.3
February 29, 2012