ISL51002_14 Datasheet, PDF (15/33 Pages) Intersil Corporation – 10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features

ISL51002
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
0x19
Red Offset LSB, (0x00)
0x1A
Green Offset MSB, (0x80)
BITS
FUNCTION NAME
5:0 N/A
7:6 Red Offset LSB
7:0 Green Offset MSB
0x1B
0x1C
Green Offset LSB, (0x00)
Blue Offset MSB, (0x80)
5:0 N/A
7:6 Green Offset LSB
7:0 Blue Offset MSB
0x1D
0x1E
0x1F
0x20
Blue Offset LSB, (0x00)
PLL Htotal MSB, (0x06)
PLL Htotal LSB, (0x98)
PLL Phase, (0x00)
5:0 N/A
7:6 Blue Offset LSB
5:0 PLL Htotal MSB
7:0 PLL Htotal LSB
5:0 PLL Sampling Phase
0x21
0x22
0x23
0x24
0x25
0x26
PLL Pre-coast, (0x04)
PLL Post-coast, (0x04)
PLL Misc, (0x00)
7:0 Pre-coast
7:0 Post-coast
0 PLL Lock Edge HSYNC
1 CLKINV ENABLE
2 Ext Coast SEL
3 Ext Coast POL
4 EXT CLOCK
DC Restore and ABLC
starting pixel MSB, (0x00)
DC Restore and ABLC
starting pixel LSB, (0x02)
DC Restore Clamp Width,
(0x10)
5:0 DC Restore and ABLC
starting pixel (MSB)
7:0 DC Restore and ABLC
starting pixel (LSB)
7:0 DC Restore clamp width
DESCRIPTION
2 LSBs of 10-bit offset word
ABLC off: upper 8-bits to Green offset DAC
ABLC enabled: Green digital offset
(See Red Offset)
See Red Offset
ABLC off: upper 8-bits to Blue offset DAC
ABLC enabled: Blue digital offset
(See Red Offset)
See Red Offset
14-bit HTOTAL. PLL updated on LSB write only.
PLL updated on LSB write only. SXGA default
Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image quality.
One step = 5.625° (1.56% of pixel period).
Number of lines the PLL will coast prior to the start of VSYNC.
Number of lines the PLL will coast after the end of VSYNC.
0: PLL locks to trailing edge of selected HSYNC (default)
1: PLL locks to leading edge of selected HSYNC
0: CLKINV input ignored
1: CLKINV input enabled
0: Internal COAST generation
1: External COAST source
0: Active high external COAST
1: Active low external COAST
0: Internal pixel clock from DPLL
1: External pixel clock from EXTCLKin pin
Pixel after Raw HSYNC trailing edge to begin DC restore and
ABLC. 14-bits.
Only applies to DC restore clamp used for AC-coupled
configurations. A value of 0x00 means the clamp DAC is never
connected to the input.
15
FN6164.3
February 29, 2012