ISL29035_14 Datasheet, PDF (9/16 Pages) Intersil Corporation – Integrated Digital Light Sensor with Interrupt

ISL29035
Read Operation
The ISL29035 has two basic read operations: Byte Read and
Burst Read.
BYTE READ
Byte read operations allow the master to access any register
location in the ISL29035. The Byte read operation is a two step
process. The master issues the START condition and the Device
Address byte with the R/W bit set to “0”, receives an
acknowledge, then issues the Register Address byte. After
acknowledging receipt of the register address byte, the master
immediately issues another START condition and the Device
Address byte with the R/W bit set to “1”. This is followed by an
acknowledge from the device and then by the 8-bit data word.
The master terminates the read operation by not responding with
an acknowledge and then issuing a stop condition (refer to
Figure 12).
BURST READ
Burst read operation is identical to the Byte Read operation.
After the first Data byte is transmitted, the master now responds
with an acknowledge, indicating it requires additional data. The
device continues to output data for each acknowledge received.
The master terminates the read operation by not responding with
an acknowledge but issuing a STOP condition (refer to Figure 13).
For more information about the I²C standard, please consult the
Phillips^™ I²C specification documents.
Power-On Reset
The Power-On Reset (POR) circuitry protects the internal logic
against powering up in the incorrect state. The ISL29035 will
power-up into Standby mode after V_DD exceeds the POR trigger
level and will power-down into Reset mode when V_DD drops
below the POR trigger level. This bidirectional POR feature
protects the device against ‘brown-out’ failure following a
temporary loss of power.
The POR is an important feature because it prevents the
ISL29035 from starting to operate with insufficient voltage, prior
to stabilization of the internal bandgap. The ISL29035 prevents
communication to its registers and greatly reduces the likelihood
of data corruption on power-up.
S
S
T
T
S
SIGNAL FROM
MASTER DEVICE
A ^{DEVICE ADDRESS}
R
WRITE
ADDRESS BYTE
A ^{DEVICE ADDRESS}
R
READ
DATA BYTE
T
O
T
T
P
SIGNAL AT SDA
10001000
10001001
SIGNALS FROM
SLAVE DEVICE
A
A
A
C
C
C
K
K
K
FIGURE 12. BYTE ADDRESS READ SEQUENCE
SIGNAL FROM
MASTER DEVICE
SIGNAL AT SDA
SIGNALS FROM
SLAVE DEVICE
S
T
A ^{DEVICE ADDRESS}
R
WRITE
T
10001000
ADDRESS BYTE
S
T
A ^{DEVICE ADDRESS}
R
READ
T
10001001
DATA BYTE 1
DATA BYTE 2
S
DATA BYTE n
T
O
P
A
A
C
C
K
K
A
A
A
C
C
C ^{(“n” is any integer}
K
K
K
greater than 1)
FIGURE 13. BURST READ SEQUENCE
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9
FN8371.1
November 12, 2014