ISL29035_14 Datasheet, PDF (11/16 Pages) Intersil Corporation – Integrated Digital Light Sensor with Interrupt

ISL29035
OPERATION MODE BITS (B5 - B7)
The ISL29035 has different operating modes. These modes are
selected by setting B5 - B7 bits on register address 0x00. The
device powers up on a disable mode. Table 6 lists the possible
operating modes.
TABLE 6. OPERATING MODES BITS
B7 B6 B5
OPERATION
0 0 0 Power-down the device (Default)
0
0
1
The device measures ALS only once every integration cycle.
This is the lowest operating mode. (Note 14)
0 1 0 IR once
0 1 1 Reserved (DO NOT USE)
1 0 0 Reserved (DO NOT USE)
1 0 1 Measures ALS continuously
1 1 0 Measures IR continuous
1 1 1 Reserved (DO NOT USE)
NOTE:
14. Intersil does not recommend using this mode.
Command-II Register (Address: 0x01)
TABLE 7. COMMAND-II REGISTER BITS
NAME
ADDR
REGISTER BITS
(Hex) B7 B6 B5 B4 B3 B2 B1
DFLT
B0 (Hex)
COMMANDII 0x01 RESERVED RES1 RES0 RANGE1 RANGE0 0x00
The Command-II register consists of ADC control bits. In this
register, there are two range bits and two ADAC resolution bits.
The default register value is 0x00 at power-on.
FULL SCALE LUX RANGE (B0 - B1)
The full scale Lux range has four different selectable ranges. The
range determines the full scale Lux range (1k, 4k, 16k, and 64k).
Each range has a maximum allowable Lux value. Lower range
values offer better resolution. Table 8 lists the possible values
of Lux.
TABLE 8. RANGE REGISTER BITS
RANGE SELECTION
B1
FULL SCALE LUX RANGE
B0
(LUX)
0
0
0
1,000
1
0
1
4,000
2
1
0
16,000
3
1
1
64,000
ADC RESOLUTION (B3 - B2)
B2 and B3 determine the ADC’s resolution and the number of
clock cycles per conversion. Changing the number of clock cycles
does more than just change the resolution of the device; it also
changes the integration time, which is the period the device’s
analog-to-digital (A/D) converter samples the photodiode current
signal for a measurement. Table 9 lists the possible ADC
resolution. Only 16bit ADC resolution can reject better 50/60Hz
noise flickering light source.
.
TABLE 9. ADC RESOLUTION DATA WIDTH
B3
B2
NUMBER OF CLOCK CYCLES n-BIT ADC
0
0
2¹⁶ = 65,536
16
0
1
2¹² = 4,096
12
1
0
2⁸ = 256
8
1
1
2⁴ = 16
4
Integration Time
TABLE 10. INTEGRATION TIME OF n-BIT ADC
n # ADC BITS
INTEGRATION TIME (ms)
4
0.0256
8
0.41
12
6.5
16
105
Data Registers (Addresses: 0x02 and 0x03)
TABLE 11. ADC REGISTER BITS
ADDR
REGISTER BITS
DFLT
NAME (Hex) B7 B6 B5 B4 B3 B2 B1 B0 (Hex)
DATA_LSB 0x02 D7 D6 D5 D4 D3 D2 D1 D0 0x00
DATA_MSB 0x03 D15 D14 D13 D12 D11 D10 D9 D8 0x00
The ISL29035 has two 8-bit read-only registers to hold the upper
and lower byte of the ADC value. The upper byte is accessed at
address 0x03 and the lower byte is accessed at address 0x02.
For 16-bit resolution, the data is from D0 to D15; for 12-bit
resolution, the data is from D0 to D11; for 8-bit resolution, the
data is from D0 to D7 and for 4-bit resolution, the data is from D0
to D3. The registers are refreshed after every conversion cycle.
The default register value is 0x00 at power-on.
TABLE 12. ADC DATA REGISTERS
ADDRESS
(HEX)
CONTENTS
0x02 D0 is LSB for 4-, 8-, 12- or 16-bit resolution; D3 is MSB for
4-bit resolution; D7 is MSB for 8-bit resolution
0x03 D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit
resolution
Lower Interrupt Threshold Registers
(Address: 0x04 and 0x05)
TABLE 13. INTERRUPT REGISTER BITS
NAME
ADDR
REGISTER BITS
DFLT
(Hex) B7 B6 B5 B4 B3 B2 B1 B0 (Hex)
INT_LT_LSB 0x04 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 0x00
INT_LT_MSB 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00
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FN8371.1
November 12, 2014