ISL29035_14 Datasheet, PDF (10/16 Pages) Intersil Corporation – Integrated Digital Light Sensor with Interrupt

ISL29035
NAME
COMMAND-I
COMMAND-II
DATA_LSB
DATA_MSB
INT_LT_LSB
INT_LT_MSB
INT_HT_LSB
INT_HT_MSB
ID
REGISTER
ADDRESS
DEC HEX
0 0x00
1 0x01
2 0x02
3 0x03
4 0x04
5 0x05
6 0x06
7 0x07
15 0x0F
TABLE 1. REGISTER MAP
B7
OP2
D7
D15
TL7
TL15
TH7
TH15
BOUT
B6
B5
OP1
OP0
RESERVED
D6
D5
D14
D13
TL6
TL5
TL14
TL13
TH6
TH5
TH14
TH13
RESERVED
1
REGISTER BITS
B4
B3
RESERVED
RES1
D4
D3
D12
D11
TL4
TL3
TL12
TL11
TH4
TH3
TH12 TH11
0
1
B2
INT
RES0
D2
D10
TL2
TL10
TH2
TH10
B1
B0
DEFAULT ACCESS
PRST1 PRST0
0x00
RW
RANGE1 RANGE0 0x00
RW
D1
D0
0x00
RO
D9
D8
0x00
RO
TL1
TL0
0x00
RW
TL9
TL8
0x00
RW
TH1
TH0
0xFF
RW
TH9
TH8
0xFF
RW
RESERVED
1x101xxx RW
Register Description
Following are detailed descriptions of the control registers
related to the operation of the ISL29035 ambient light sensor
device. These registers are accessed by the I²C serial interface.
For details on the I²C interface, refer to “Serial Interface” on
page 7.
All the features of the device are controlled by the registers. The
ADC data can also be read. The following sections explain the
details of each register bit. All RESERVED bits are Intersil used
bits ONLY. The value of the reserved bit can change without
notice.
Decimal to Hexadecimal Conversion
To convert decimal value to hexadecimal value, divide the
decimal number by 16, and write the remainder on the side as
the least significant digit. This process is continued by dividing
the quotient by 16 and writing the remainder until the quotient
is 0. When performing the division, the remainders, which will
represent the hexadecimal equivalent of the decimal number,
are written beginning with the least significant digit (right) and
each new digit is written to the next more significant digit (the
left) of the previous digit. Consider the number 175 decimal.
TABLE 2. DECIMAL TO HEXADECIMAL
DIVISION
QUOTIENT
REMAINDER HEX NUMBER
175/16
10 = A
15 = F
0xAF
Command-I Register (Address: 0x00)
TABLE 3. COMMAND-I REGISTER ADDRESS
NAME
ADDR
REGISTER BITS
(Hex) B7 B6 B5 B4 B3 B2 B1
DFLT
B0 (Hex)
COMMANDI 0x00 OP2 OP1 OP0 RESERVED INT PRST1 PRST0 0x00
The Command-I register consists of control and status bits. In
this register, there are two interrupt persist bits, one interrupt
status bit, and three operation mode bits. The operation mode
bits and the interrupt persist bits are independent of each other.
The default register value is 0x00 at power-on.
INTERRUPT PERSIST BITS (B0 - B1)
The interrupt persist bits provide control over when interrupts
occur. There are four different selections for this feature. A value
of n (where n is 1, 4, 8, and 16) results in an interrupt only if the
value remains outside the threshold window for n consecutive
integration cycles. For example, if n is equal to 16 and the ADC
resolution is set to 16-bits, then the integration time is 105ms.
An interrupt is generated whenever the last conversion results in
a value outside of the programmed threshold window. The
interrupt is active-low and remains asserted until cleared by
writing the COMMAND register with the CLEAR bit set. Table 4
lists the possible interrupt persist bits.
TABLE 4. INTERRUPT PERSIST BITS
NUMBER OF INTEGRATION
B1
B0
CYCLES (n)
0
0
1
0
1
4
1
0
8
1
1
16
INTERRUPT STATUS BIT (B2)
The interrupt status bit (INT) is a status bit for light intensity
detection. The bit is set to logic HIGH when the light intensity
crosses the interrupt thresholds window (register address
0x04 - 0x07), and set to logic LOW when it is within the interrupt
thresholds window. Once the interrupt is triggered, the INT pin
goes low and the interrupt status bit goes HIGH until the status
bit is polled through the I²C read command. Both the INT pin and
the interrupt status bit are automatically cleared at the end of
the 8-bit Device Register byte (0x00) transfer. Table 5 shows the
interrupt status states.
BIT 2
0
1
TABLE 5. INTERRUPT STATUS BIT (INT)
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
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FN8371.1
November 12, 2014